To maintain compatibility with older versions of Make, suffix rules can be defined. They are a poor man's style of pattern rules. An example of a double suffix rule is:
.c.o:
$(CC) -c $(CFLAGS) -o $@ $<
.SUFFIXES: .c .o
The above suffix rule defines how to make any target with a filename ending in .o if there is a corresponding dependent filename that ends in .c. The commands associated with a suffix rule are executed if the dependent file is newer than the target file.
A suffix rule has no dependencies listed to the right of the colon. If such dependencies exist, then the rule definition is considered to be an ordinary target rule.
The .SUFFIXES directive is used to cause the Make program to find all ordinary rules that can be interpreted as suffix rules matching the suffix arguments. Each suffix rule is transformed into its equivalent pattern rule at this time.