Parts list and building details for SAPEP v2.0 All these parts are stocked items at any Active Componants (Canada), or Future Electronics (USA). Everything (except for the ZIF socket) should cost under $20 bucks. The file PARTS.PIC shows pinouts for all the parts. -- Logic Chips -- All chips are HC or HCT. Sub LS at your own risk. U1 74HC08 Quad AND Gates U2-4 7407 Hex Hi-V OC Buffers NOT HC/T! U5 74HC74 Dual D-Type Flip Flop U6 74HC138 3 to 8 Demultiplexer U7-9 74HC139 Dual 2 to 4 Demultiplexer U10 74HC244 Octal Line Driver U11 74HC245 Octal BiDir Bus Driver U12-15 74HC574 Octal D-Type Latch -- Diodes -- D1 T-1 led RED (Socket Busy) D2 T-1 led GREEN (Socket Free) D3 T-1 led YELLOW (Programming) D4 T-1 led RED (SAPEP Power) D5-10 1N914 (Signal Diode) BR1 Bridge Rectifier 1 amp DIP type -- Transistors -- Q1 2N4401 Q2 - Q7 2N4403 -- Capacitors -- C1 470uf 35 volts C2 1uf 32 volts C3 220uf 10 volts C4 22uf 10 volts C5 22uf 25 volts -- Resistors -- All resistors 1/4w & 1% R1 - R4 330 ohm R5 - R6 470 ohm R7 - R10 1k ohm R11- R20 10k ohm R21 330 ohm R22 360 ohm R23 70 ohm R24 150 ohm R25 1400 ohm R26 2430 ohm R27- R28 365 ohm R29 100 ohm R30 100 ohm R31 3k ohm R32- R33 10k ohm -- Misc -- REG1 LM7805 1A (Circuit Power) Heat Sink for REG1 REG2 -3 LM317 500ma (Variable Volts) ZIF SOCKET 32 pin Zero Insertion Force Socket ($$) J1 Suitible power jack PS1 Power Supply AC or DC! Max 25vdc/24vac. See text Male DB25 connector OR Centronics Perfboard or copper clad circuit board. -- How It Works Part 1: Computer Interface -- Because this unit can be connected to a long parallel cable, some type of buffering/driving system must be in place. Chips U10 & U11 do just that. U10 is an octal buffer, and U11 is an octal buffer/driver. A cable of upto 6 feet (2m) can be usind to attach the hardware to the computer. All data lines are either INPUT or OUTPUT. The three access lines (Busy/Pout/Sel) are always outputs. They are buffered by 1/2 of U10, then the buffered signals go into U6 which is a 3 to 8 decoder. When you write/read a byte to the parallel port, _STROBE goes low for 1.4us. This will strobe 1 of the 8 outputs of U6. One half of U7 controlls the actions of U11. One action (direction) is decided upon the state of the three access lines. If all are LOW, then Y0 will go low, and data will flow from SAPEP to the computer, otherwise, data flows from the computer to SAPEP. The other action is isolation. When Busy/Pout/Sel are all high, U11 isolates the computer's data lines from the data lines found in SAPEP. This works out very well, from a safty point of view. No conflicts will occur if you try and print with SAPEP plugged in. -- How It Works Part 2: Data Storage -- All data is stored in 4 74HC574 Octal latches. U12, U13 and half of U14 store the 20 address lines (A0-A19) that goto the ZIF socket. The other half of U14 and all of U15 route timing signals, set voltages, and configure the socket. A short synopsis of the functions are: Chip bits Function U12 0 - 7 Address lines A0 to A7 U13 0 - 7 Address lines A7 to A15 U14 0 - 3 Address lines A16 to A19 4 & 5 Which pin gets the program pulse 6 & 7 Which pin has Vcc on it U15 0 - 2 Which pin has Vpp on it 3 & 4 Sets Vcc to 5.00, 6.00, 6.25 or 6.50v 5 - 7 Sets Vpp to 12.00, 12.50, 12.75, 13.00 or 21.00v Part of U5 also acts as a storage register. When reading a chip (not verifying it), this register contains 0 (It is indirectly hooked up to _E). Most other times, it is kept at logic 1. -- How It Works Part 3: The Timer -- A time period of 100us to 78ms is generated by CIA-A inside the Amiga. This proved to be the most accurate time source. The other half of U5 is set up like a toggle flip-flop. The basic operation is like this: Write the low address bytes to U12 (this SETs the FF to a 1) Kill the Amiga multi-tasking Set the access lines to access the timer FF Write the 16bit timer value to the time registers - timer is now counting at 1 count every 1.4us Send the 8bit value to be programmed to the parallel port - The timer FF has now been strobed, and it's output goes low Wait in a loop for timer to signal it's done - During this time the eprom is burning in the written byte When loop is done, READ the parallel port. Data stays the same, but we have strobed the timer FF again, bringing it's output HIGH. The data byte is now burned into the eprom. Which pin gets the pulsed signal is decided by part of U7. Because some PGM pins are address lines on different sized eproms, they must still be capable of going HIGH or LOW. The AND gates of U1 allow this to happen. -- How It Works Part 4: Setting Voltages -- The key to this project is the ability to adjust the voltages needed by the eprom to all the industry standards. The two voltage regulators have several resistors from thier ADJ pins to ground. Grounding the junction of any two resistors will change the regulators output voltage. The open-collector buffers are used for this grounding task. With a logic 1 as the input, they are basicly disconnected from any voltage (very much like a 3 stated bus). A logic 0 grounds the outputs. A normal TTL gate CANNOT be used for this task. These resistor ladders act like multi-tap pots. The values given are common resistor values. The actual output voltages should be within 5% of the following: Vcc supply 5.00v 6.00v 6.25v 6.50v Vpp supply 12.00v 12.50v 12.75v 13.00v 21.00v The calibration routines in the software will help you to fine-tune the voltages (assuming you used a pot here and there), although the output should be just fine. *NOTE The buffers add a small amount of resistance when they ground a signal. Even 50 ohms can cause a .2v difference. I suggest that if you attempt to mix and match your own resistor values, you use a buffer gate to get a real-world voltage value. -- How It Works Part 5: Who Gets What -- U9 selects which pins get what signals. Depending upon the eprom size, a pin might be Vcc, PGM, Address, Vpp or _G. The transistors 'switch' in a higher voltage to the circuit (this could be anywhere from 5 to 21v). Diodes protect TTL outputs from the higher voltages. For example, look at Q8. If Y3 of controlling half of U9 is low, then Z24 will have whatever voltage Vpp is set to (12 to 21v). But D10 protects the AND gate from this potential killer voltage (no matter what state the AND gate puts out). If Y3 goes to a '1', that high volatage will no longer appear at the TTL/HiV junction. Now the TTL side of the diode determines the logic level. The diode does drop .7v, so if the TTL part puts out a logic 1 at 5.00v, the voltage on the other side of the diode will be 4.30v. I suggest using HC or HCT parts because thier outputs sit closer to 5v than LS parts. This is important when the signal must go over a diode. -- How It Works Part 6: Status LEDs -- Three of the four LEDs are driven through U10. The 74HC244 can sink/source more current than other parts in this circuit. D4 is powered directly from the main circuit's +5v supply. See the software docs on what all these LEDs mean. -- How It Works Part 7: Power Supply -- One of the great things about this project is the power supply required. It can be AC or DC, and if you choose DC, the plug polarity doesn't matter! BR1 can be 4 diodes, or a 4 pin DIP package. I like using DIP packages, they take less space, and are simpler to connect. Depending on what you intend to do with this project, you can select the adapter accordingly. Task Eprom type Use READ (no sig) Any kind Min 6vdc/6.3vac unregulated 300ma READ/WRITE Vpp of 12-13v Min 12vdc/12.6vac unregulated 400ma READ/WRITE Vpp of 12-21v Min 24vdc/25.2vac unregulated 500ma * Note * The adapter voltages may vary according to what family TTL chips you use. My all-HC/HCT version pulled 215ma from the 5v supply. Add another 100ma for the eprom's power and programming currents. I suggest you use a CSA/UL rated adapter. Radio Shack is a good place to look. If you're handy with HIGH VOLTAGE, then rig up your own AC supply. Just be careful if you do decide to build your own, and keep the transformer OFF the SAPEP board (or well isolated). Can't afford to lose any of you guys ;-) -- Other Things You Should Know -- There is NO printed circuit board for this project. I will do one as soon as I can find the time, but that might not be for a few months. My version fits on 4 bread boards (JUST fits). Using perfboard will work fine. All registered owners of SAPEP will receive a copy of the artwork when it becomes availible. There are no decoupling caps for each chip. Because of the slow switching nature of the project, caps aren't needed. The printed circuit version WILL have the caps though. You MUST use a good heat-sink on REG1. Even though no more than 300ma of current is used, it tends to get hot FAST! When chips have 2 have DUAL functions (Like the 74HC139), it doesn't matter which side you use for whatever function. For example, if your board layout makes it simpler to combine half of U8's & U9's functions on the same chip, that's just fine. - EOF -