| From: | Almos Rajnai |
| Date: | 18 Jul 2000 at 08:20:16 |
| Subject: | Re: Run68k yet a trouble |
Hello once again!
On 17 Jul 00, at 21:49, Frank Wille wrote:
> > Why should I place into the .tocd section?
> for PPC. Currently you will need
>
> lwz r11,@__PowerPCBase(r2)
That is for because _PowerPCBase located in the data segment of the
68k, and I did not merged together -> only the address is in the TOC
area. (It is not possible to force 68k data area to the TOC? Of
course without merging all togteher.) But you were right, I will move
it into the TOC.
> A section is not PPC cache aligned, which means 32-bytes aligned.
That was really a suprise to me. It is not mentioned anywhere in the
developer docs, and may cause dangerous cache underruns. Why does
loadseg not patched in some way then?
> Sigh. Yes, vlink will merge everything, if you force it to do so.
> But with this style your programs may never get larger than 64k. ;)
I have some experience with multiple data segments... It is a must on
intel... ;) (I hate that dumb processor...) So, I manage the merging
trough two-three linking passes, not all the stuff merged together.
> mflr r0
> stw r0,8(r1) # save LR in caller's stack frame
> stwu r1,-160(r1) # new SF: 160 bytes should be enough
160 bytes? 32 not enough? What is the exact value?
> What? The code which my fd2libWOS generates, makes a perfect
> PowerOpen stack frame.
Sorry then, I probably missed it.
> Sorry, but this feature is still missing. Maybe in a future
> release. I have plans for pasm V2, a portable assembler for
> multiple CPUs and object file formats.
I am keen on waiting!
> Please send me an example source and I will try to fix it.
Ok, I will.
Thanks for your answer again, I learned a lot.
Bye:
Almos Rajnai
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