| From: | Jesse McClusky |
| Date: | 12 Sep 2000 at 09:41:17 |
| Subject: | Re: AMIOPEN: has anyone run SPEC benchmark using VP?] |
> From: <mef@cs.washington.edu>
>
> Jesse McClusky writes:
> >3D-Now is AMD. SIMD is Intel.
>
> Speaking of which. Does anyone have an idea of how one might "enhance" the
> VP architecture description to include some sort of vector instructions?
Tao needs to add processor another number for each (3D-Now and SIMD),
and provide an optimizing translator for both. I suspect they're working on
one right now, but I don't know this for sure. There is a lot of other stuff
they have on their plate...
> My thought here is that a translator that is aware of the native processor
> enhancements, such as AMD's 3D-Now or Motorola's Altivec for the PowerPC,
> could then "maybe" produce those native instructions from the VP-vector
> instructions. This, of course, would require that people code up various
> routines directly in VP assembler, as I am not aware of GCC or any other
> compiler doing this automatically for you.
These types of instructions are *always* written in assembler, even
in applications, just usually native assembler and not VP. I do rather
suspect though that they might not add extra instructions, but rather
simply be able to detect certain patterns in code and convert them to
optimized native code within the translator. This would be ideal,
because it would mean that other existing code would now suddenly
be translated into those optimized instructions as well, giving a
speed-up almost anywhere possible.
> Hmmmm.... then again, maybe this isn't such a great idea, as I suppose
> rather than doing this all at the VP level, people will simply provide
> "native" tools that are fine tuned to a particular architecture's features.
This is always an option. However, the architecture has to be able
to know the difference, and right now the tool loader doesn't
differentiate between a PII, Celeron, PIII, and an Athelon.
Jesse
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