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c64 circuit theory

[sERIAL INTERFACE AND USER PORT SCHEMATIC]
tHE sERIAL iNTERFACE AND uSER pORT cIRCUITS
tHE sERIAL iNTERFACE.
u2 IS A cOMPLEX iNTERFACE aDAPTER (cia). pARALLEL PORT SIGNALS pa3-pa7 CONTROL THE SERIAL BUS INTERFACE. pa3 IS THE aTTENTION (atn) OUTPUT. tHIS SIGNAL IS INVERTED BY u8 BEFORE BEING TRANSMITTED TO A DEVICE ON THE BUS. pa4 IS THE CLOCK OUTPUT. dATA TRANSMITTED FROM THE c64 TO A DEVICE ON THE BUS IS SYNCHRONIZED BY THIS CLOCK SIGNAL. u8 INVERTS THE OUTPUT pa4. pa5 IS THE DATA OUTPUT. u8 INVERTS THIS OUTPUT ALSO. dATA TRANSMITTED FROM A DEVICE ON THE BUS TO THE c64 IS SYNCHRONIZED BY A CLOCK GENERATED BY THE TRANSMITTING DEVICE. tHE cLOCK SIGNAL IS INPUT ON pa6. dATA TRANSMITTED FROM A DEVICE ON THE BUS TO THE c64 IS INPUT ON pa7. wHEN A DEVICE ON THE BUS WANTS TO COMMUNICATE WITH THE c64, sqr in GOES "LOW" INDICATING SERVICE IS REQUESTED.
tHE uSER pORT
pARALLEL PORT b OF u2 (pb0 - pb7) IS MADE AVAILABLE ON THE USER PORT. pARALLEL DATA TRANSFERS WITH EXTERNAL DEVICE ARE MADE VERY EASILY THROUGH THIS PARALLEL PORT. sp2 AND sp1 ARE BI-DIRECTIONAL SERIAL PORTS. cnt1 AND cnt2 ARE BI-DIRECTIONAL SYNCHRONIZING CLOCK SIGNALS FOR EACH SERIAL BUS.
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tHIS PAGE HAS BEEN CREATED BY sAMI rAUTIAINEN.
lAST UPDATED fEBRUARY 11, 1998.
rEAD THE SMALL PRINT.