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1541 circuit theory
![[rESET lOGIC SCHEMATIC]](/file/7055/cbm-funet-archive-2003.iso/cbm/schematics/drives/new/1541/service/small/Page_06.gif)
tHE rESET cIRCUIT
tHE OUTPUT OF THE EXCLUSIVE 'OR' GATE ud3 PIN 6 WILL BE "LOW" UNTIL c46 HAS
CHARGED THROUGH r25. oNCE THE VOLTAGE ACROSS c46 REACHES 2 VOLTS, THE OUTPUT OF
ud3 PIN 6 WILL GO "HIGH". tHIS OCCURS WHEN THE DISK IS POWERED ON, OR A RESET
PULSE IS GENERATED BY A DEVICE CONNECTED TO THE SERIAL BUS. tHE RESET PULSE ON
THE SERIAL BUS INTERFACE IS INPUT ON, PIN 6 OF p2 OR p3. tHIS "LOW" TO "HIGH"
GOING PULSE ON PIN 6 OF ud3 IS INPUT TO THE MICROPROCESSORS RESET INTERRUPT
INPUT. tHIS CAUSES A RESTART ON RESET ROUTINE TO BE EXECUTED GIVING CONTROL OF
THE DISK DRIVE OPERATION TO THE dISK oPERATING sYSTEM (dos).
tHIS PAGE HAS BEEN CREATED BY sAMI rAUTIAINEN.
lAST UPDATED aPRIL 18, 1998.
rEAD THE SMALL PRINT.
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