40 pin | 42 pin | desc | function |
1 | 1 | test | iNPUT USED IN DESIGN VERIFICATION. |
2-9 | 2-9 | yb0-yb7 | dATA INPUT/OUTPUT LINES FOR READ/WRITE OPERATION. |
10 | 10 | vSS | gROUND. |
11,12 | 11,12 | stp0,stp1 | iNPUT TO STEPPER DRIVER. |
13 | 13 | mtr | cONTROL LINE USED TO ACTIVATE THE STEPPER MOTOR. |
14 | 14 | a | wRITE PROTECT INPUT. iNDICATES DISK IS WRITE PROTECTED. |
15,16 | 15,16 | ds0,ds1 | iNPUTS USED TO PRODUCE THE BINARY COUNT FOR THE FREQUENCY DIVIDE RATIO. |
17 | 17 | sync | sYNC OUTPUT. |
18 | 18 | ted | a LOW INPUT CLEARS THE byte LINE IN 2 mhZ MODE. a HIGH SETS 1541 MODE. |
19 | 19 | oe | iNPUT TO READ/WRITE BLOCK TO SET MODE. 0 FOR wRITE, 1 FOR rEAD. |
20 | 20 | accl | iNPUT SELECT LINE FOR THE cpu CLOCK. 0 FOR 1541 - 1 mhZ, 1 FOR 1571 - 2 mhZ. |
xx | 21,22 | | n/c |
21 | 23 | osc | 16 mhZ CLOCK INPUT. |
22 | 24 | atna | aTTENTION ACKNOWLEDGE INPUT. |
23 | 25 | atni | aTTENTION LINE INPUT FROM SERIAL BUS. |
24 | 26 | atn | aTTENTION DATA INPUT FROM SERIAL BUS. |
25-28 | 27-30 | y0-y3 | cONTROL OUTPUT LINES FOR THE 4 PHASES OF THE STEPPER MOTOR. |
29 | 31 | xrw | ram WRITE ENABLE OUTPUT. |
30 | 32 | vCC | +5vdc. |
31 | 33 | clr | hIGH INPUT WHEN THE READ DATA IS LOGICAL 1. |
32 | 34 | pll | iNPUT FROM THE 20 PIN GATE ARRAY. cLOCK COMPENSATION. |
33 | 35 | lock | iNDICATES THE pll lock STATUS. wHEN LOGICAL 1, pll IS LOCKED. wHEN 0, THE INTERNAL CLOCK IS USED FOR SAMPLING DATA. |
34 | 36 | r/w | r/w SELECT INPUT. |
35,36 | 37,38 | q,qX | wRITE PULSE OUTPUTS. |
37 | 39 | ck | cLOCK SELECT OUTPUT - 1 OR 2 mhZ. |
38 | 40 | b | wRITE ENABLE OUTPUT. |
39 | 41 | soe | eNABLE BYTE INPUT. |
40 | 42 | byte | dATA LATCHED OUTPUT. |