DP Tool Club 3/CDASC03.ISO/sorties/314/hardware.txt

Text File | 1993-04-01 | 132KB | 3,332 lines

@Hardware Data and Specifications                Copyright 1991 David Jurgens
:6845:CRTC
^6845 - Motorola CRT Controller

    3B0-3BB Monochrome Monitor Adapter
    3D0-3DC Color Graphics Adapter (mapped similarly)

    3B0/3D0  port address decodes to 3B4/3D4
    3B1/3D1  port address decodes to 3B5/3D5
    3B2/3D2  port address decodes to 3B4/3D4
    3B3/3D3  port address decodes to 3B5/3D5
    3B4/3D4  6845 index register, selects which register [0-11h]
         is to be accessed through port 3B5/3D5
    3B5/3D5  6845 data register [0-11h] selected by port 3B4/3D4,
         registers 0C-0F may be read.  If a read occurs
         without the adapter installed, FFh is returned.
    3B6/3D6  port address decodes to 3B4/3D4
    3B7/3D7  port address decodes to 3B5/3D5
    3B8/3D8  6845 mode control register
    3B9/3D9  color select register on color adapter
    3BA/3DA  status register (read only)
    3BB/3DB  light pen strobe reset
        3DC  preset light pen latch
        3DF  CRT/CPU page register (PCjr only)

%    Registers: Accessed through ports 3B5 & 3D5    VALID VALUES
%                            MONO CO40 CO80 GRPH
    00 - Horiz. total characters             61   38   71   38
    01 - Horiz. displayed characters per line    50   28   50   28
    02 - Horiz. synch position             52   2D   5A   2D
    03 - Horiz. synch width in characters         0F   0A   0A   0A
    04 - Vert. total lines                 19   1F   1F   7F
    05 - Vert. total adjust (scan lines)         06   06   06   06
    06 - Vert. displayed rows             19   19   19   64
    07 - Vert. synch position (character rows)   19   1C   1C   70
    08 - Interlace mode                 02   02   02   02
    09 - Maximum scan line address             0D   07   07   01
    0A - Cursor start (scan line)             0B   06   06   06
    0B - Cursor end (scan line)             0C   07   07   07
    0C - Start address (MSB)             00   00   00   00
    0D - Start address (LSB)             00   00   00   00
    0E - Cursor address (MSB) (read/write)         00   --   --   --
    0F - Cursor address (LSB) (read/write)         00   --   --   --
    10 - Light pen (MSB)   (read only)         --   --   --   --
    11 - Light pen (LSB)   (read only)         --   --   --   --

    - Registers 00-0D are write only, registers 0E-0F are read/write and
      registers 10-11 are read only
    - Cursor address is calculated with using the following (row*80)+col

^6845 - Port 3B8 (Monochrome)

    │7│6│5│4│3│2│1│0│  3B8 CRT Control Port
     │ │ │ │ │ │ │ └──── 1 = 80x25 text
     │ │ │ │ │ └─┴───── unused
     │ │ │ │ └──────── 1 = enable video signal
     │ │ │ └───────── unused
     │ │ └────────── 1 = blinking on
     └─┴─────────── unused

^6845 - Port 3D8 (Color)

    │7│6│5│4│3│2│1│0│  3D8 Mode Select Register
     │ │ │ │ │ │ │ └──── 1 = 80x25 text, 0 = 40x25 text
     │ │ │ │ │ │ └───── 1 = 320x200 graphics, 0 = text
     │ │ │ │ │ └────── 1 = B/W, 0 = color
     │ │ │ │ └─────── 1 = enable video signal
     │ │ │ └──────── 1 = 640x200 B/W graphics
     │ │ └───────── 1 = blink, 0 = no blink
     └─┴────────── unused

^6845 - Port 3D9 Color Text Modes

    │7│6│5│4│3│2│1│0│  3D9 Color Select Register (3B9 not used)
     │ │ │ │ │ └─┴─┴──── screen/border RGB
     │ │ │ │ └───────── select intensity setting
     │ │ │ └────────── background intensity
     └─┴─┴─────────── unused

^6845 - Port 3D9 Color Graphics Modes

    │7│6│5│4│3│2│1│0│  3D9 Color Select Register (3B9 not used)
     │ │ │ │ │ └─┴─┴──── RGB for background
     │ │ │ │ └───────── intensity
     │ │ │ └────────── unused
     │ │ └─────────── 1 = palette 1, 0=palette 0 (see below)
     └─┴──────────── unused

      Palette 0 = green, red, brown
      Palette 1 = cyan, magenta, white

^6845 - Port 3DA  Status Register

    │7│6│5│4│3│2│1│0│  3DA Status Register
     │ │ │ │ │ │ │ └──── 1 = display enable, RAM access is OK
     │ │ │ │ │ │ └───── 1 = light pen trigger set
     │ │ │ │ │ └────── 0 = light pen on, 1 = light pen off
     │ │ │ │ └─────── 1 = vertical retrace, RAM access OK for next 1.25ms
     └─┴─┴─┴──────── unused
:765:FDC:NEC 765:8272:floppy controller
^NEC µPD765  -    Floppy Disk Controller    -  8272A

%    PS/2 FDC Diskette Status Register A at 3F0h

    │7│6│5│4│3│2│1│0│  3F0h  PS/2 Disk Status Register A (read-only)
     │ │ │ │ │ │ │ └──── direction
     │ │ │ │ │ │ └───── write protect
     │ │ │ │ │ └────── index
     │ │ │ │ └─────── head 1 select
     │ │ │ └──────── track 0
     │ │ └───────── step
     │ └────────── second drive installed
     └─────────── interrupt pending

%    PS/2 FDC Diskette Status Register B at 3F1h

    │7│6│5│4│3│2│1│0│  3F1h  PS/2 Disk Status Register B (read-only)
     │ │ │ │ │ │ │ └──── motor enable 0
     │ │ │ │ │ │ └──── motor enable 1
     │ │ │ │ │ └──── write enable
     │ │ │ │ └──── read data (toggles w/positive transition in -RD DATA)
     │ │ │ └──── write data (toggles w/positive transition in WR DATA)
     │ │ └──── drive select
     └─┴──── reserved

%    FDC Digital Output Register at 3F2h  (all systems)

    │7│6│5│4│3│2│1│0│  port 3F2h  (write only)
     │ │ │ │ │ │ └─┴──── floppy drive select (0=A, 1=B, 2=floppy C, ...)
     │ │ │ │ │ └─────── 1 = FDC enable, 0 = hold FDC at reset
     │ │ │ │ └──────── 1 = DMA & I/O interface enabled  (reserved PS/2)
     │ │ │ └───────── 1 = turn floppy drive A motor on
     │ │ └────────── 1 = turn floppy drive B motor on
     │ └─────────── 1 = turn floppy drive C motor on; (reserved PS/2)
     └──────────── 1 = turn floppy drive D motor on; (reserved PS/2)

    - used to control drive motors, drive selection, and feature enable
    - PS/2 only uses bit 0 for floppy drive select; bit 1 is reserved
    - PS/2 only uses bits 5 & 4 for  motor enable; bits 7&6 are reserved
    - all DOR bits are cleared during controller reset

%    FDC Main Status Register at 3F4h  (all systems)

    │7│6│5│4│3│2│1│0│  port 3F4h  (read only)
     │ │ │ │ │ │ │ └──── floppy drive 0 in seek mode/busy
     │ │ │ │ │ │ └───── floppy drive 1 in seek mode/busy
     │ │ │ │ │ └────── floppy drive 2 in seek mode/busy (reserved PS/2)
     │ │ │ │ └─────── floppy drive 3 in seek mode/busy (reserved PS/2)
     │ │ │ └──────── FDC read or write command in progress
     │ │ └───────── FDC is in non-DMA mode
     │ └────────── I/O direction;  1 = FDC to CPU; 0 = CPU to FDC
     └─────────── data reg ready for I/O to/from CPU (request for master)

%    FDC Command Status Register 0 at 3F5h  (all systems)

    │7│6│5│4│3│2│1│0│  Command Status Register 0 at port 3F5h
     │ │ │ │ │ │ └─┴──── unit selected at interrupt (0=A, 1=B, 2=...)
     │ │ │ │ │ └─────── head number at interrupt (head 0 or 1)
     │ │ │ │ └──────── not ready on read/write or SS access to head 1
     │ │ │ └───────── equipment check (see note)
     │ │ └────────── set to 1 when FDD completes a seek command
     └─┴─────────── last command status (see below)

%    Bits
%     76  Last Command Status
     00  command terminated successfully
     01  command execution started but terminated abnormally
     10  invalid command issued
     11  command terminated abnormally due to a change in state of
         the Ready Signal from the FDC  (reserved on PS/2)

    - equipment check can occur if FDD signals a fault or track zero is
      not found after 77 steps on a recalibrate command
    - PS/2 only uses bits 1-0 for drive (values are 01b and 10b)

%    FDC Command Status Register 1 at 3F5h  (all systems)

    │7│6│5│4│3│2│1│0│  Command Status Register 1 at port 3F5h
     │ │ │ │ │ │ │ └──── FDC cannot find ID address mark (see reg 2)
     │ │ │ │ │ │ └───── write protect detected during write
     │ │ │ │ │ └────── FDC cannot find sector ID
     │ │ │ │ └─────── unused (always zero)
     │ │ │ └──────── over-run;  FDC not serviced in reasonable time
     │ │ └───────── data error (CRC) in ID field or data field
     │ └────────── unused (always zero)
     └─────────── end of cylinder; sector# greater than sectors/track

    - bit 0 of Status Register 1 and bit 4 of Status Register 2 are
      related and mimic each other

%    FDC Command Status Register 2 at 3F5h  (all systems)

    │7│6│5│4│3│2│1│0│  Command Status Register 2 at port 3F5h
     │ │ │ │ │ │ │ └──── missing address mark in data field
     │ │ │ │ │ │ └───── bad cylinder, ID not found and Cyl Id=FFh
     │ │ │ │ │ └────── scan command failed, sector not found in cylinder
     │ │ │ │ └─────── scan command equal condition satisfied
     │ │ │ └──────── wrong cylinder detected
     │ │ └───────── CRC error detected in sector data
     │ └────────── sector with deleted data address mark detected
     └─────────── unused (always zero)

    - bit 0 of Status Register 1 and bit 4 of Status Register 2 are
      related and mimic each other

%    FDC Command Status Register 3 at 3F5h (FDD status, all systems)

    │7│6│5│4│3│2│1│0│  Floppy Disk Drive Status at port 3F5h
     │ │ │ │ │ │ └─┴──── FDD unit selected status (0=A, 1=B, 2=...)
     │ │ │ │ │ └─────── FDD side head select status (0=head 0, 1=head 1)
     │ │ │ │ └──────── FDD two sided status signal
     │ │ │ └───────── FDD track zero status signal
     │ │ └────────── FDD ready status signal
     │ └─────────── FDD write protect status signal
     └──────────── FDD fault status signal

%    FDC Digital Input Register at 3F7h (AT & PS/2)

    │7│6│5│4│3│2│1│0│  3F7h  Digital Input Register (read only)
     │ │ │ │ │ │ │ └─── high density select
     │ └─┴─┴─┴─┴─┴──── reserved
     └─────────────── diskette change

%    FDC Configuration Control Register at 3F7h (AT & PS/2)

    │7│6│5│4│3│2│1│0│  3F7h  Configuration Control Register (write only)
     │ │ │ │ │ │ └─┴── DRC1, DRC0  (see below)
     └─┴─┴─┴─┴─┴───── reserved

    DRC1 DRC0
      0   0    500000 bit per second mode
      0   1    reserved
      1   0    250000 bit per second mode
      1   1    reserved


    - Digital Input Register is used to sense the state of the
      (-diskette change) and the (-high density select) signals
    - Configuration Control Register is used to set the transfer rate


^FDC Programming Considerations

%    Three phases of command execution:

    1.  Command phase; commands are sent from the CPU to the FDC via
        port 3F5h;    bit 6 of the Status Register at 3F4h must be zero
    2.  Execution phase; FDC executes instruction & generates INT 6
    3.  Result phase; status and other information is available to CPU;
        INT 6 sets bit 7 of BIOS Data Area location 40:3E which can
        be polled for completion status


%    Example of a read operation:

    1. turn disk motor on and set delay time for drive spin up
    2. perform seek operation;  wait for disk interrupt
    3. prepare DMA chip to move data to memory
    4. send read command and wait for transfer complete interrupt
    5. read status information
    6. turn disk motor off


^Floppy Diskette Controller Operations (15 commands)

%    Read Data       D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF  SK    0   0    1   1    0
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    data length (if cmd byte 5==0)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Read Deleted Data  D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF  SK    0   1    1   0    0
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    data length (if cmd byte 5==0)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Write Data       D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF   0    0   0    1   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    data length (if cmd byte 5==0)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Write Deleted Data D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF   0    0   1    0   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    data length (if cmd byte 5==0)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Read a Track       D7  D6  D5  D4  D3  D2  D1  D0
%    (Diagnostic)
    command byte 0:     0  MF  SK    0   0    0   1    0
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    data length (if cmd byte 5==0)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Read ID        D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:     0  MF   0    0   1    0   1    0
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Format a Track       D7  D6  D5  D4  D3  D2  D1  D0
%    (Write Sector IDs)
    command byte 0:     0  MF   0    0   1    1   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    bytes per sector
    command byte 3:    sectors per track
    command byte 4:    gap 3 length
    command byte 5:    filler pattern to write in each byte
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Scan Equal       D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF  SK    1   0    0   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    scan test (1=scan contiguous, 2=scan alternate)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Scan Low or Equal  D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF  SK    1   1    0   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    scan test (1=scan contiguous, 2=scan alternate)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Scan High or Equal D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:    MT  MF  SK    1   1    1   0    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    cylinder number
    command byte 3:    head number
    command byte 4:    sector number
    command byte 5:    bytes per sector
    command byte 6:    end of track (last sector in track)
    command byte 7:    gap 3 length
    command byte 8:    scan test (1=scan contiguous, 2=scan alternate)
    result byte 0:       status register 0
    result byte 1:       status register 1
    result byte 2:       status register 2
    result byte 3:       cylinder number
    result byte 4:       head number
    result byte 5:       sector number
    result byte 6:       bytes per sector

%    Recalibrate       D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:     0    0   0    0   0    1   1    1
    command byte 1:     ?    ?   ?    ?   ?    0  US1 US0
    returns nothing

%    Sense Interrupt    D7  D6  D5  D4  D3  D2  D1  D0
%        Status
    command byte 0:     0    0   0    0   1    0   0    0
    result byte 0:       status register 0
    result byte 1:       present cylinder number

%    Specify Step &       D7  D6  D5  D4  D3  D2  D1  D0
%      Head Load
    command byte 0:     0    0   0    0   0    0   1    1
    command byte 1:    step rate time │ head unload time
    command byte 2:    ──────head load time──────    ND
    returns nothing

%    Sense Drive       D7  D6  D5  D4  D3  D2  D1  D0
%      Status
    command byte 0:     0    0   0    0   0    1   0    0
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    result byte 0:       status register 3

%    Seek           D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:     0    0   0    0   1    1   1    1
    command byte 1:     ?    ?   ?    ?   ?  HD  US1 US0
    command byte 2:    new cylinder number
    returns nothing

%    µPD765 Version       D7  D6  D5  D4  D3  D2  D1  D0

    command byte 0:     ?    ?   ?    1   0    0   0    0
    result byte 0:       status register 0
               90h = µPD765B;  80h = µPD765A or µPD765A-2

%    Invalid Command

    result byte 0:       status register 0 (value of 80h)


%    Key to Abbreviations
    HD = Head Number Selected    SK = SKip Deleted-data address mark
    MT = Multi-Track        US0 = drive select bit 0
    MF = MFM mode            US1 = drive select bit 1
    ND = Non-DMA mode

    Head Load Time = 2 to 254ms in 2ms increments
    Head Unload Time = 16 to 240ms in 16ms increments
    Step Rate Time = 1 to 16ms in 1ms increments


    - PS/2 systems use the 8272A diskette controller which is software
      and port compatible with the NEC µPD765
    - accessed through ports 3F0h-3F7h;  NEC µPD765 is accessed through
      ports 3F2h, 3F4h and 3F5h;   the 8272A uses ports 3F0h, 3F1h,
      3F2h, 3F4h, 3F5h and 3F7h
    - data, command and status registers are all accessed through
      port 3F5h a register stack with one address presented to the bus
    - bit 7 of BIOS Data Area byte 40:3E can be polled to determine
      if a disk operation has completed;  this bit is set by the
      interrupt handler when the operation has completed;  it should
      be reset before continuing on with the next FDC operation

    - see  ~BIOS Data Area~   ~INT TABLE~   ~INT 13~

:8042:keyboard controller
^8042 - Keyboard Controller  (AT,PS/2)

%    8042 Status Register (port 64h read)

    │7│6│5│4│3│2│1│0│  8042 Status Register
     │ │ │ │ │ │ │ └──── output register (60h) has data for system
     │ │ │ │ │ │ └───── input register (60h/64h) has data for 8042
     │ │ │ │ │ └────── system flag (set to 0 after power on reset)
     │ │ │ │ └─────── data in input register is command (1) or data (0)
     │ │ │ └──────── 1=keyboard enabled, 0=keyboard disabled (via switch)
     │ │ └───────── 1=transmit timeout (data transmit not complete)
     │ └────────── 1=receive timeout (data transmit not complete)
     └─────────── 1=even parity rec'd, 0=odd parity rec'd (should be odd)

%    Port Mode          Description

    64h  read   8042 status register. Can be read at any time.  See
            table above for more information.
    64h  write  8042 command register.  Writing this port sets Bit 3
            of the status register to 1 and the byte is treated
            as a controller command.  Devices attached to the
            8042 should be disabled before issuing commands that
            return data since data in the output register will
            be overwritten.
    60h  read   8042 output register (should only be read if Bit 0 of
            status port is set to 1)
    60h  write  8042 data register.  Data should only be written if
            Bit 1 of the status register is zero (register is empty).
            When this port is written Bit 3 of the status register
            is set to zero and the byte is treated as a data.  The
            8042 uses this byte if it's expecting data for a previous
            command, otherwise the data is written directly to the
            keyboard.    See ~KEYBOARD COMMANDS~ for information on
            programming the actual keyboard hardware.


^8042 Commands Related to PC Systems  (Port 64h)

%    Command            Description

     20   Read 8042 Command Byte: current 8042 command byte is placed
          in port 60h.
     60   Write 8042 Command Byte: next data byte written to port 60h is
          placed in 8042 command register.    Format:

         │7│6│5│4│3│2│1│0│    8042 Command Byte
          │ │ │ │ │ │ │ └──── 1=enable output register full interrupt
          │ │ │ │ │ │ └───── should be 0
          │ │ │ │ │ └────── 1=set status register system, 0=clear
          │ │ │ │ └─────── 1=override keyboard inhibit, 0=allow inhibit
          │ │ │ └──────── disable keyboard I/O by driving clock line low
          │ │ └───────── disable auxiliary device, drives clock line low
          │ └────────── IBM scancode translation 0=AT, 1=PC/XT
          └─────────── reserved, should be 0

     A4   Password Installed Test: returned data can be read
          from port 60h;  FA=password installed, F1=no password
     A5   Load Security: bytes written to port 60h will be read
          until a null (0) is found.
     A6   Enable Security: works only if a password is already loaded
     A7   Disable Auxiliary Interface: sets Bit 5 of command register
          stopping auxiliary I/O by driving the clock line low
     A8   Enable Auxiliary Interface: clears Bit 5 of command register
     A9   Auxiliary Interface Test: clock and data lines are tested;
          results placed at port 60h are listed below:

        00  no error
        01  keyboard clock line is stuck low
        02  keyboard clock line is stuck high
        03  keyboard data line is stuck low
        04  keyboard data line is stuck high

     AA   Self Test: diagnostic result placed at port 60h, 55h=OK
     AB   Keyboard Interface Test:    clock and data lines are tested;
          results placed at port 60h are listed above with command A9
     AC   Diagnostic Dump: sends 16 bytes of 8042's RAM, current input
          port state, current output port state and 8042 program status
          word to port 60h in scan-code format.
     AD   Disable Keyboard Interface: sets Bit 4 of command register
          stopping keyboard I/O by driving the clock line low
     AE   Enable Keyboard Interface: clears Bit 4 of command register
          enabling keyboard interface.
     C0   Read Input Port: data is read from its input port (which is
          inaccessible to the data bus) and written to output register
          at port 60h;  output register should be empty before call.

           │7│6│5│4│3-0│  8042 Input Port
        │ │ │ │ └──── undefined
        │ │ │ └───── 1=enable 2nd 256K of motherboard RAM, 0=disable
        │ │ └────── 1=manufacturing jumper not installed, 0=installed
        │ └─────── 1=primary display is MDA, 0=primary display is CGA
        └──────── 1=keyboard not inhibited, 0=keyboard inhibited

     C1   Poll Input Port Low Bits: Bits 0-3 of port 1 placed in
          status Bits 4-7
     C2   Poll Input Port High Bits: Bits 4-7 of port 1 placed in
          status Bits 4-7
     D0   Read Output Port: data is read from 8042 output port (which is
          inaccessible to the data bus) and placed in output register;
          the output register should be empty.  (see command D1 below)
     D1   Write Output Port: next byte written to port 60h is placed in
          the 8042 output port (which is inaccessible to the data bus)

        │7│6│5│4│3│2│1│0│  8042 Output Port
         │ │ │ │ │ │ │ └──── system reset line
         │ │ │ │ │ │ └───── gate A20
         │ │ │ │ └─┴────── undefined
         │ │ │ └───────── output buffer full
         │ │ └────────── input buffer empty
         │ └─────────── keyboard clock (output)
         └──────────── keyboard data (output)

     D2   Write Keyboard Output Register: on PS/2 systems the next data
          byte written to port 60h input register is written to port 60h
          output register as if initiated by a device; invokes interrupt
          if enabled
     D3   Write Auxiliary Output Register: on PS/2 systems the next data
          byte written to port 60h input register is written to port 60h
          output register as if initiated by a device; invokes interrupt
          if enabled
     D4   Write Auxiliary Device: on PS/2 systems the next data byte
          written to input register a port at 60h is sent to the
          auxiliary device
     E0   Read Test Inputs: 8042 reads its T0 and T1 inputs; data is
          placed in output register;  Bit 0 is T0, Bit 1 is T1:

        │1│0│  Test Input Port Bits
         │ └──── keyboard clock
         └───── keyboard data

     Fx   Pulse Output Port: Bits 0-3 of the 8042 output port can be
          pulsed low for 6 µs;  Bits 0-3 of command indicate which
          Bits should be pulsed; 0=pulse, 1=don't pulse; pulsing
          Bit 0 results in CPU reset since it is connected to system
          reset line.

    - PC systems previous to the AT use the 8255 PPI as a keyboard
      controller and use the keyboard's internal 8048.
    - the keyboard's internal controller buffers up to 16 bytes of
      make/break code information.    This is common among all PC systems
      and shouldn't be confused with the (32 byte) keyboard buffer
      maintained by the BIOS.
    - see  ~KEYBOARD COMMANDS~ for information on programming the
      keyboards internal microprocessor
:8250:16450:16550:UART
^UART - Universal Asynchronous Receiver/Transmitter

%     Port            Description

    3F8/2F8   Transmit/Receive Buffer  (read/write)
          Baud Rate Divisor LSB if bit 7 of LCR is set    (read/write)
    3F9/2F9   IER - Interrupt Enable Register  (read/write)
          Baud Rate Divisor MSB if bit 7 of LCR is set    (read/write)
    3FA/2FA   IIR - Interrupt Identification Register  (read only)
          FCR - 16550 FIFO Control Register  (write only)
    3FB/2FB   LCR - Line Control Register  (read/write)
    3FC/2FC   MCR - Modem Control Register    (read/write)
    3FD/2FD   LSR - Line Status Register  (read only)
    3FE/2FE   MSR - Modem Status Register  (read only)
    3FF/2FF   Scratch Pad Register    (read/write)


^Detailed UART Description

%   Port 3F8/2F8 - Transmit/Receive Buffer  (read/write)
%           Baud Rate Divisor LSB if bit 7 of LCR is set  (read/write)

%   Port 3F9/2F9 - Interrupt Enable Register - IER  (read/write)
%           Baud Rate Divisor MSB if bit 7 of LCR is set  (read/write)

    │7│6│5│4│3│2│1│0│  3F9, 2F9: Interrupt Enable Register
     │ │ │ │ │ │ │ └──── 1 = enable data available int (and 16550 Timeout)
     │ │ │ │ │ │ └───── 1 = enable THRE interrupt
     │ │ │ │ │ └────── 1 = enable lines status interrupt
     │ │ │ │ └─────── 1 = enable modem-status-change interrupt
     └─┴─┴─┴──────── reserved (zero)

    - 16550 will interrupt if data exists in the FIFO and isn't read
      within the time it takes to receive four bytes or if no data is
      received within the time it takes to receive four bytes.


^Baud Rate Divisor Table

%              Baud Rate                 Baud Rate
%    Baud Rate           Divisor           Baud Rate      Divisor

      50        900h          2400        30h
     110        417h          3600        20h
     150        300h          4800        18h
     300        180h          7200        10h
     600         C0h          9600        0Ch
    1200         60h         19200        06h
    1800         40h         38400        03h
    2000         3Ah        115200        01h

    - Baud rate divisors can be calculated by taking the oscillating
      frequency (1,843,200) and dividing by the quantity of the desired
      baud rate times the UART clocking factor (16).  Use the following
      formula:
^divisor = 1843200 / (BaudRate * 16);


^Port 3FA/2FA - Interrupt Identification Register - IIR  (read only)

    │7│6│5│4│3│2│1│0│  3FA, 2FA Interrupt ID Register
     │ │ │ │ │ │ │ └──── 1 = no int. pending, 0=int. pending
     │ │ │ │ │ └─┴───── Interrupt Id bits (see below)
     │ │ │ │ └──────── 16550  1 = timeout int. pending, 0 for 8250/16450
     │ │ └─┴───────── reserved (zero)
     └─┴──────────── 16550    set to 1 if FIFO queues are enabled

%    Bits
%     21      Meaning         Priority        To reset
     00  modem-status-change      lowest      read MSR
     01  transmit-register-empty  low      read IIR / write THR
     10  data-available          high      read rec buffer reg
     11  line-status          highest      read LSR

    - interrupt pending flag uses reverse logic, 0 = pending, 1 = none
    - interrupt will occur if any of the line status bits are set
    - THRE bit is set when THRE register is emptied into the TSR


^Port 3FA/2FA - 16550 FIFO Control Register - FCR  (write only)

    │7│6│5│4│3│2│1│0│  3FA, 2FA  FIFO Control Register
     │ │ │ │ │ │ │ └──── 1 = enable clear XMIT and RCVR FIFO queues
     │ │ │ │ │ │ └───── 1 = clear RCVR FIFO
     │ │ │ │ │ └────── 1 = clear XMIT FIFO
     │ │ │ │ └─────── 1 = change RXRDY & TXRDY pins from mode 0 to mode 1
     │ │ └─┴──────── reserved (zero)
     └─┴─────────── trigger level for RCVR FIFO interrupt

%    Bits      RCVR FIFO
%     76    Trigger Level
     00       1 byte
     01       4 bytes
     10       8 bytes
     11      14 bytes

    - Bit 0 must be set in order to write to other FCR bits
    - Bit 1 when set to 1 the RCVR FIFO is cleared and this bit is reset.
      The receiver shift register is not cleared.
    - Bit 2 when set to 1 the XMIT FIFO is cleared and this bit is reset.
      The transmit shift register is not cleared.


^Port 3FB/2FB - Line Control Register - LCR  (read/write)

    │7│6│5│4│3│2│1│0│  3FB, 2FB  Line Control Register
     │ │ │ │ │ │ └─┴──── word length select bits (see below)
     │ │ │ │ │ └─────── 0 = 1 stop bit, 1 = 1.5 or 2  (see note)
     │ │ │ │ └──────── 0 = no parity, 1 = parity (PEN)
     │ │ │ └───────── 0 = odd parity, 1 = even (EPS)
     │ │ └────────── 0 = parity disabled, 1 = enabled
     │ └─────────── 0 = turn break off, 1 = force spacing break state
     └──────────── 1 = baud rate divisor (DLAB); 0 = RBR, THR or IER

%    Bits
%     10    Word length bits
     00 = 5 bits per character
     01 = 6 bits per character
     10 = 7 bits per character
     11 = 8 bits per character

    - stop bits = 1.5 for 5 bit words or 2 for 6, 7 or 8 bit words
    - bit 7 changes the mode of registers 3F8 and 3F9.  If set these
      registers become the LSB and MSB of the baud rate divisor.
      Otherwise 3F8 is the Transmit/Receive Buffer Register and 3F9 is
      the Interrupt Enable Register.


^Port 3FC/2FC - Modem Control Register - MCR  (read/write)

    │7│6│5│4│3│2│1│0│  3FC, 2FC  Modem Control Register
     │ │ │ │ │ │ │ └──── 1 = activate DTR
     │ │ │ │ │ │ └───── 1 = activate RTS
     │ │ │ │ │ └────── OUT1
     │ │ │ │ └─────── OUT2
     │ │ │ └──────── 0 = normal, 1 = loop back test
     └─┴─┴───────── reserved (zero)

    - If bit 4 is set, data from the Transmit Shift Register is received
      in the Receiver Shift Register.  The SOUT line is set to logic
      high, the SIN line and control lines are disconnected.   CTS, DSR,
      RI and CD inputs are disconnected.  DTR, RTS, OUT1 and OUT2 are
      then connected internally.
    - some communications nodes require RTS and DTR to be raised
      separately.


^Port 3FD/2FD - Line Status Register - LSR  (read only)

    │7│6│5│4│3│2│1│0│  3FD, 2FD Line Status Register
     │ │ │ │ │ │ │ └──── 1 = data ready
     │ │ │ │ │ │ └───── 1 = overrun error (OE)
     │ │ │ │ │ └────── 1 = parity error (PE)
     │ │ │ │ └─────── 1 = framing error (FE)
     │ │ │ └──────── 1 = break interrupt  (BI)
     │ │ └───────── 1 = transmitter holding register empty (THRE)
     │ └────────── 1 = transmitter shift register empty (TSRE)
     └─────────── 1 = 16550 PE/FE/Break in FIFO queue, 0 for 8250 & 16450

    - Bit 0 is set when a byte is placed in the Receiver Buffer Register
      and cleared when the byte is read by the CPU (or when the CPU
      clears the FIFO for the 16550).  Results in Receive Data Available
      Interrupts if enabled.
    - Bits 1-4 indicate errors and result in Line Status Interrupts
      if enabled.
    - Bit 1 is set when a second byte is received before the byte
      in the Receiver Buffer Register is read by the CPU (the 16550 in
      FIFO mode sets this bit when the queue is full and the byte in the
      Receiver Shift Register hasn't been moved into the queue).  This
      bit is reset when the CPU reads the LSR
    - Bit 2 is set whenever a byte is received that doesn't match the
      requested parity.  Reset upon reading the LSR.  (The 16550 maintains
      parity information with each byte and sets bit 2 only when the byte
      is at the top of the FIFO queue.)
    - Bit 3 is set when a character is received without proper stop
      bits.  Upon detecting a framing error the UART attempts to
      resynchronize.  Reset by reading the LSR.  (The 16550 maintains
      this information with each byte and sets bit 3 only when the byte
      is at the top of the FIFO queue.)
    - Bit 4 is set when a break condition is sensed (when space is
      detected for longer than 1 fullword).  A zero byte is placed in
      the Receiver Buffer Register (or 16550 FIFO).  Reset by reading
      the LSR.  (The 16550 maintains this information with each byte and
      sets bit 4 only when the byte is at the top of the FIFO queue.)
    - Bit 5 is set when the Transmit Holding Register shifts a byte
      into the Transmit Shift Register (or XMIT FIFO queue is empty for
      16550) and is cleared when a byte is written to the THR (or the
      XMIT FIFO).    Results in Transmit Holding Register Empty interrupts
      if enabled.
    - Bit 6 is set when both the Transmitter Holding Register and the
      Transmitter Shift Register are empty. On the 16550, when the XMIT
      FIFO and Transmitter Shift Register are empty.
    - Bit 7 is 16550 specific and indicates there is a byte in the FIFO
      queue that was received with a Parity, Framing or Break error.


^Port 3FE/2FE - Modem Status Register - MSR (read only)

    │7│6│5│4│3│2│1│0│  3FE, 2FE Modem Status Register
     │ │ │ │ │ │ │ └──── 1 = DCTS  Delta CTS  (CTS changed)
     │ │ │ │ │ │ └───── 1 = DDSR  Delta DSR  (DSR changed)
     │ │ │ │ │ └────── 1 = RI ring indicator changed
     │ │ │ │ └─────── 1 = DDCD  Delta Data Carrier Detect (DCD changed)
     │ │ │ └──────── 1 = CTS
     │ │ └───────── 1 = DSR
     │ └────────── 1 = ring indicator (RI)
     └─────────── 1 = receive line signal detect

    - Bits 0-3 are reset when the CPU reads the MSR
    - Bit 4 is the Modem Control Register RTS during loopback test
    - Bit 5 is the Modem Control Register DTR during loopback test
    - Bit 6 is the Modem Control Register OUT1 during loopback test
    - Bit 7 is the Modem Control Register OUT2 during loopback test

^Port 3FF/2FF - Scratch Pad Register  (read/write)

%    Programming considerations:
    - 8250's, 16450's are essentially identical to program
    - 16550's is pin and software compatible with the 16450 but has an
      internal FIFO queue that may be enabled/disabled by software
    - PCs are capable of 38.4Kb, while AT's are capable of 115.2Kb
    - receiver checks only the first stop bit of each character regardless
      of the number of stop bits specified
    - Older 8250 and 16450 UARTs may lose THRE interrupt if the THRE and
      Receive Data (RD) or the Line Status (LS) interrupts occur
      simultaneously during a full duplex transmission.  RD and LS have
      higher priority than THRE which causes the lower priority interrupt
      to be lost.  The following are 3 methods used to avoid this problem:

      1. Disable/re-enable THRE interrupt via the IER after processing
         Receive Data & Line Status interrupts.
      2. While inside the RD and LS interrupt routines check the LSR
         THRE bit and set a flag that a THRE interrupt was waiting.
      3. Poll the LSR THRE bit instead of using the IIR.

    - data loss can occur without overrun or framing errors if the
      interrupts are serviced too slowly
    - reserved bits are usually set to zero.  Code should NOT rely on
      this being the case since future enhancement may use these bits
    - see  ~INT TABLE~  or  ~IRQ~  for interrupt assignments
    - see  ~PORTS~   for COMx port assignment (3F8,2F8,3E8,2E8,3220...)
:8253:8254:PIT:timer
^8253/8254 PIT - Programmable Interval Timer

    Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
    Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
    Port 42h, 8253 Counter 2 Cassette and Speaker Functions
    Port 43h, 8253 Mode Control Register, data format:

    │7│6│5│4│3│2│1│0│  Mode Control Register
     │ │ │ │ │ │ │ └──── 0=16 binary counter, 1=4 decade BCD counter
     │ │ │ │ └─┴─┴───── counter mode bits
     │ │ └─┴────────── read/write/latch format bits
     └─┴───────────── counter select bits (also 8254 read back command)

%    Bits
%     76 Counter Select Bits
     00  select counter 0
     01  select counter 1
     10  select counter 2
     11  read back command (8254 only, illegal on 8253, see below)

%    Bits
%     54  Read/Write/Latch Format Bits
     00  latch present counter value
     01  read/write of MSB only
     10  read/write of LSB only
     11  read/write LSB, followed by write of MSB

%    Bits
%    321  Counter Mode Bits
    000  mode 0, interrupt on terminal count;  countdown, interrupt,
         then wait for a new mode or count; loading a new count in the
         middle of a count stops the countdown
    001  mode 1, programmable one-shot; countdown with optional
         restart; reloading the counter will not affect the countdown
         until after the following trigger
    010  mode 2, rate generator; generate one pulse after 'count' CLK
         cycles; output remains high until after the new countdown has
         begun; reloading the count mid-period does not take affect
         until after the period
    011  mode 3, square wave rate generator; generate one pulse after
         'count' CLK cycles; output remains high until 1/2 of the next
         countdown; it does this by decrementing by 2 until zero, at
         which time it lowers the output signal, reloads the counter
         and counts down again until interrupting at 0; reloading the
         count mid-period does not take affect until after the period
    100  mode 4, software triggered strobe; countdown with output high
         until counter zero;  at zero output goes low for one CLK
         period;  countdown is triggered by loading counter;  reloading
         counter takes effect on next CLK pulse
    101  mode 5, hardware triggered strobe; countdown after triggering
         with output high until counter zero; at zero output goes low
         for one CLK period

%    Read Back Command Format  (8254 only)

    │7│6│5│4│3│2│1│0│ Read Back Command (written to Mode Control Reg)
     │ │ │ │ │ │ │ └─── must be zero
     │ │ │ │ │ │ └──── select counter 0
     │ │ │ │ │ └───── select counter 1
     │ │ │ │ └────── select counter 2
     │ │ │ └─────── 0 = latch status of selected counters
     │ │ └──────── 0 = latch count of selected counters
     └─┴───────── 11 = read back command

%    Read Back Command Status (8254 only, read from counter register)

    │7│6│5│4│3│2│1│0│  Read Back Command Status
     │ │ │ │ │ │ │ └─── 0=16 binary counter, 1=4 decade BCD counter
     │ │ │ │ └─┴─┴──── counter mode bits (see Mode Control Reg above)
     │ │ └─┴───────── read/write/latch format (see Mode Control Reg)
     │ └──────────── 1=null count (no count set), 0=count available
     └───────────── state of OUT pin (1=high, 0=low)


    - the 8253 is used on the PC & XT, while the 8254 is used on the AT+
    - all counters are decrementing and fully independent
    - the PIT is tied to 3 clock lines all generating 1.19318 MHz.
    - the value of 1.19318MHz is derived from (4.77/4 MHz) and has its
      roots based on NTSC frequencies
    - counters are 16 bit quantities which are decremented and then
      tested against zero.    Valid range is (0-65535).  To get a value
      of 65536 clocks you must specify 0 as the default count since
      65536 is a 17 bit value.
    - reading by latching the count doesn't disturb the countdown but
      reading the port directly does; except when using the 8254 Read
      Back Command
    - counter 0 is the time of day interrupt and is generated
      approximately 18.2 times per sec.  The value 18.2 is derived from
      the frequency 1.10318/65536 (the normal default count).
    - counter 1 is normally set to 18 (dec.) and signals the 8237 to do
      a RAM refresh approximately every 15µs
    - counter 2 is normally used to generate tones from the speaker
      but can be used as a regular counter when used in conjunction
      with the 8255
    - newly loaded counters don't take effect until after a an output
      pulse or input CLK cycle depending on the mode
    - the 8253 has a max input clock rate of 2.6MHz, the 8254 has max
      input clock rate of 10MHz

%    Programming considerations:

      1.  load Mode Control Register
      2.  let bus settle (jmp $+2)
      3.  write counter value
      4.  if counter 0 is modified, an INT 8 handler must be written to
          call the original INT 8 handler every 18.2 seconds.  When it
          does call the original INT 8 handler it must NOT send and EOI
          to the ~8259~ for the timer interrupt, since the original INT 8
          handler will send the EOI also.

%    Example code:

    countdown  equ    8000h ; approx 36 interrupts per second

       cli
       mov    al,00110110b  ; bit 7,6 = (00) timer counter 0
                  ; bit 5,4 = (11) write LSB then MSB
                  ; bit 3-1 = (011) generate square wave
                  ; bit 0 = (0) binary counter
       out    43h,al          ; prep PIT, counter 0, square wave&init count
       jmp    $+2
       mov    cx,countdown  ; default is 0x0000 (65536) (18.2 per sec)
                  ; interrupts when counter decrements to 0
       mov    al,cl          ; send LSB of timer count
       out    40h,al
       jmp    $+2
       mov    al,ch          ; send MSB of timer count
       out    40h,al
       jmp    $+2
       sti
:8259:PIC
^8259  Programmable Interrupt Controller  (PIC)

%    Initialization Command Word 1 at Port 20h and A0h

    │7│6│5│4│3│2│1│0│  ICW1
     │ │ │ │ │ │ │ └──── 1=ICW4 is needed, 0=no ICW4 needed
     │ │ │ │ │ │ └───── 1=single 8259, 0=cascading 8259's
     │ │ │ │ │ └────── 1=4 byte interrupt vectors, 0=8 byte int vectors
     │ │ │ │ └─────── 1=level triggered mode, 0=edge triggered mode
     │ │ │ └──────── must be 1 for ICW1 (port must also be 20h or A0h)
     └─┴─┴───────── must be zero for PC systems

%    Initialization Command Word 2 at Port 21h and A1h

    │7│6│5│4│3│2│1│0│  ICW2
     │ │ │ │ │ └─┴─┴──── 000= on 80x86 systems
     └─┴─┴─┴─┴───────── A7-A3 of 80x86 interrupt vector

%    Initialization Command Word 3 at Port 21h and A1h

    │7│6│5│4│3│2│1│0│  ICW3 for Master Device
     │ │ │ │ │ │ │ └──── 1=interrupt request 0 has slave, 0=no slave
     │ │ │ │ │ │ └───── 1=interrupt request 1 has slave, 0=no slave
     │ │ │ │ │ └────── 1=interrupt request 2 has slave, 0=no slave
     │ │ │ │ └─────── 1=interrupt request 3 has slave, 0=no slave
     │ │ │ └──────── 1=interrupt request 4 has slave, 0=no slave
     │ │ └───────── 1=interrupt request 5 has slave, 0=no slave
     │ └────────── 1=interrupt request 6 has slave, 0=no slave
     └─────────── 1=interrupt request 7 has slave, 0=no slave

    │7│6│5│4│3│2│1│0│  ICW3 for Slave Device
     │ │ │ │ │ └─┴─┴──── master interrupt request slave is attached to
     └─┴─┴─┴─┴───────── must be zero

%    Initialization Command Word 4 at Port 21h and A1h

    │7│6│5│4│3│2│1│0│  ICW4
     │ │ │ │ │ │ │ └──── 1 for 80x86 mode, 0 = MCS 80/85 mode
     │ │ │ │ │ │ └───── 1 = auto EOI, 0=normal EOI
     │ │ │ │ └─┴────── slave/master buffered mode (see below)
     │ │ │ └───────── 1 = special fully nested mode (SFNM), 0=sequential
     └─┴─┴────────── unused (set to zero)

%    Bits
%     32    Buffering Mode
     00    not buffered
     01    not buffered
     10    buffered mode slave (PC mode)
     11    buffered mode master (PC mode)

%    Operation Control Word 1 / Interrupt Mask Reg.    (Ports 21h & A1h)

    │7│6│5│4│3│2│1│0│  OCW1 - IMR Interrupt Mask Register
     │ │ │ │ │ │ │ └──── 0 = service IRQ0, 1 = mask off
     │ │ │ │ │ │ └───── 0 = service IRQ1, 1 = mask off
     │ │ │ │ │ └────── 0 = service IRQ2, 1 = mask off
     │ │ │ │ └─────── 0 = service IRQ3, 1 = mask off
     │ │ │ └──────── 0 = service IRQ4, 1 = mask off
     │ │ └───────── 0 = service IRQ5, 1 = mask off
     │ └────────── 0 = service IRQ6, 1 = mask off
     └─────────── 0 = service IRQ7, 1 = mask off

%    Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h)

    │7│6│5│4│3│2│1│0│  OCW2 - ICR Interrupt Command Register
     │ │ │ │ │ └─┴─┴──── interrupt request level to act upon
     │ │ │ │ └───────── must be 0 for OCW2
     │ │ │ └────────── must be 0 for OCW2
     └─┴─┴─────────── EOI type (see table)

%    Bits
%    765  EOI - End Of Interrupt code (PC specific)
    001  non-specific EOI command
    010  NOP
    011  specific EOI command
    100  rotate in automatic EOI mode
    101  rotate on non-specific EOI command
    110  set priority command  (uses bits 2-0)
    111  rotate on specific EOI command

%    Operation Control Word 3   (Ports 20h & A0h)

    │7│6│5│4│3│2│1│0│  OCW3
     │ │ │ │ │ │ │ └─── 1=read IRR on next read, 0=read ISR on next read
     │ │ │ │ │ │ └──── 1=act on value of bit 0, 0=no action if bit 0 set
     │ │ │ │ │ └───── 1=poll command issued, 0=no poll command issued
     │ │ │ │ └────── must be 1 for OCW3
     │ │ │ └─────── must be 0 for OCW3
     │ │ └──────── 1=set special mask, 0=reset special mask
     │ └───────── 1=act on value of bit 5, 0=no action if bit 5 set
     └────────── not used (zero)

%    Other Registers

    IRR - Interrupt Request Register, maintains a bit vector indicating
          which IRQ hardware events are awaiting service.    Highest
          level interrupt is reset when the CPU acknowledges interrupt.
    ISR - In Service Register, tracks IRQ line currently being serviced.
          Updated by EOI command.


^Hardware Interrupt Sequence of Events:

    1. 8259 ~IRQ~ signal is raised high by hardware setting the
       corresponding IRR bits true.

    2. PIC evaluates the interrupt requests and signals the CPU
       where appropriate.

    3. CPU acknowledges the INT by pulsing INTA (inverted)

    4. INTA signal from CPU is received by the PIC, which then sets the
       highest priority ISR bit, and clears the corresponding IRR bit

    5. CPU sends a second INTA pulse which causes the PIC to send the
       interrupt ID byte onto the bus.  CPU begins interrupt processing.

    6. Interrupts of lower and equal priority are blocked until a
       Non-Specific EOI (20h) is sent to the command port.


^Initialization Procedure

%    Initialization
     1. write ICW1 to port 20h
     2. write ICW2 to port 21h
     3. if ICW1 bit D1=1  do nothing
        if ICW1 bit D1=0  write ICW3 to port 20h
     4. write ICW4 to port 21h
     5. OCW's can follow in any order


^8259 Programmable Interrupt Controller Notes

    - Operation Command Word (OCW), commands that set the 8259 in
      various interrupt modes.  These can be written to the 8259
      anytime after initialization.
    - The 8259 differentiates between the OCW1, OCW2 and OCW3 by the
      port address and the value of the data bits D4 and D3.  ICW2
      through ICW4 are order related and must follow ICW1.    ICW1 is
      identified by an even port number and data bit D4 set to 1.
    - PCs operate in fully nested mode, where a Non-Specific EOI resets
      the interrupt identified by the highest bit value in the ISR
    - 8259s can be chained together where the INT pin (output) of a
      slave 8259 can be used as the input to an IRQ line allowing up
      to 64 priority vectored interrupts.  AT level machines use two
      8259's for a total of 16 hardware interrupt levels
    - the first 8259 ports are located at 20h and 21h
    - the second 8259 ports are located at A0h and A1h
    - PC and AT interrupts are Edge Triggered while PS/2's are Level
      Triggered
    - some ASIC chips designed for Tandy 1000 Systems malfunction if
      specific and non-specific EOIs are mixed
    - for a more in-depth discussion of the 8259, see Intel's "Micro-
      processor and Peripherals Handbook, Volume I"

    - see  ~PORTS~  and  ~INT TABLE~
:BUS
^PC, XT and AT 8 bit BUS Structure

                   ┌────────┐
               Ground ─┤B1    A1├─ -I/O CH CHK (NMI)
           +Reset DRV ─┤B2    A2├─ +Data 7
              +5V ─┤B3    A3├─ +Data 6
            +IRQ2 ─┤B4    A4├─ +Data 5
              -5V ─┤B5    A5├─ +Data 4
            +DRQ2 ─┤B6    A6├─ +Data 3
             -12V ─┤B7    A7├─ +Data 2
          -CARD SLCTD ─┤B8    A8├─ +Data 1
             +12V ─┤B9    A9├─ +Data 0
               Ground ─┤B10  A10├─ +I/O CH RDY
            -MEMW ─┤B11  A11├─ +AEN
            -MEMR ─┤B12  A12├─ +Address 19
             -IOW ─┤B13  A13├─ +Address 18
             -IOR ─┤B14  A14├─ +Address 17
               -DACK3 ─┤B15  A15├─ +Address 16
            +DRQ3 ─┤B16  A16├─ +Address 15
               -DACK1 ─┤B17  A17├─ +Address 14
            +DRQ1 ─┤B18  A18├─ +Address 13
        -DACK0 (MREF) ─┤B19  A19├─ +Address 12
              CLK ─┤B20  A20├─ +Address 11
            +IRQ7 ─┤B21  A21├─ +Address 10
            +IRQ6 ─┤B22  A22├─ +Address 9
            +IRQ5 ─┤B23  A23├─ +Address 8
            +IRQ4 ─┤B24  A24├─ +Address 7
            +IRQ3 ─┤B25  A25├─ +Address 6
               -DACK2 ─┤B26  A26├─ +Address 5
              +TC ─┤B27  A27├─ +Address 4
             +ALE ─┤B28  A28├─ +Address 3
              +5V ─┤B29  A29├─ +Address 2
             +OSC ─┤B30  A30├─ +Address 1
               Ground ─┤B31  A31├─ +Address 0
                   └────────┘

^AT 16 Bit BUS Extension

                   ┌────────┐
            -MEM CS16 ─┤D1    C1├─ SBHE
            -I/O CS16 ─┤D2    C2├─ Address 23
            IRQ10 ─┤D3    C3├─ Address 22
            IRQ11 ─┤D4    C4├─ Address 21
            IRQ12 ─┤D5    C2├─ Address 20
            IRQ15 ─┤D6    C6├─ Address 19
            IRQ14 ─┤D7    C7├─ Address 18
               -DACK0 ─┤D8    C8├─ Address 17
             DRQ0 ─┤D9    C9├─ -MEMR
               -DACK5 ─┤D10  C10├─ -MEMW
             DRQ5 ─┤D11  C11├─ Data 8
               -DACK6 ─┤D12  C12├─ Data 9
             DRQ6 ─┤D13  C13├─ Data 10
               -DACK7 ─┤D14  C24├─ Data 11
             DRQ7 ─┤D15  C15├─ Data 12
              +5V ─┤D16  C16├─ Data 13
              -Master ─┤D17  C17├─ Data 14
               Ground ─┤D18  C18├─ Data 15
                   └────────┘

    - pin numbering starts from the rear of the machine


%     Signal             Description

    A0-A19         Address Bits 0-19 allow access to 1Mb memory and 64K of
             port addresses.
    A17-A23      Address Bits 17-23 allow access from 1Mb memory to 16Mb
    AEN         Address Enable; When active the DMA controller has
             control of the Address and Data BUS as well as the
             MEMR/MEMW lines. When inactive the CPU has control of
             these lines
    ALE         Address Latch Enable (output); used to latch addresses
             from the CPU.  Forced active during DMA cycles.
    CARD SLCTD   Card Selected; activated by cards in the XT's slot 8
    CLK         System clock signal (actual BUS speed)
    D0-D7         Data bits 0-7 for I/O to memory and I/O
    DACK0-DACK3  DMA Acknowledge for channels 0-3; used by the controller
             to acknowledge DMA requested.  DACK0 is used for memory
             refresh (MREF)
    DRQ0-DRQ3    DMA Request 0-3; used by peripherals to get service from
             the DMA controller;  Held active until the corresponding
             DACKx signal becomes active.
    I/O CH CHK   I/O Channel Check; Generates a Non Maskable Interrupt
    I/O CH RDY   I/O Channel Ready; pulled inactive my memory or I/O
             devices to lengthen memory or I/O cycles.    Usually used
             by slower devices to add wait states.  Should not be
             held inactive for more than 17 cycles.
    I/O CS16     I/O Chip Select 16 Bit; 16 bit I/O cycle
    IOR         I/O Read; instructs an I/O device to drive its data
             onto the system BUS
    IOW         I/O Write; instructs an I/O device to read data from
             the BUS
    IRQ2-IRQ7    Interrupt Requests 2-7; signals the CPU that an I/O
             device needs service  (see ~8259~)
    MASTER         Used with DRQ to gain control of system
    MEM CS16     Memory Chip Select 16 Bit; 16 Bit memory cycle
    MEMR         Memory Read; this signal is driven by the CPU or DMA
             controller and instructs memory to drive its data onto
             the system BUS.  Present on both PC and AT extension BUS
    MEMW         Memory Write;  this signal is driven by the CPU or DMA
             controller and instructs memory to read and store data
             from the system BUS.  Present on both PC and AT
             extension BUS
    OSC         Oscillator; 14.31818 MHz clock (70ns period); 50% duty
             cycle
    RESET DRV    Reset Drive; used to reset system logic
    SBHE         System BUS High Enable; activates data bits 8-15 on AT
             extension BUS
    TC         Terminal Count; pulses when the terminal count for a
             DMA channel is reached


    - all ISA BUS signals use standard TTL levels
    - input and output are relative to the CPU
:capacitor values
^Ceramic File Capacitor Color Code Chart

%         Color     Digit     Multiplier

         Black     0      1
         Brown     1      10
         Red     2      100         Gold      ± 5% tolerance
         Orange     3      1,000      Silver   ±10% tolerance
         Yellow     4      10,000     White      ±10% tolerance
         Green     5      100,000
         Blue     6      1,000,000
         Violet     7
         Gray     8
         White     9

%         ╒═████░██▒██▓██░██▒████═╕
%         ┴                 ┴
           │  │  │  │  │
           │  │  │  └──┴─────── tolerance/temperature dependance
           │  │  └─────────── picofarad value multiplier
           └──┴──────────── first 2 digits of picofarad value
:CMOS RAM:CMOS clock:RTC
^CMOS RTC - Real Time Clock and Memory (ports 70h & 71h)

%    Reg#              Description

     00  RTC seconds
     01  RTC seconds alarm
     02  RTC minutes
     03  RTC minutes alarm
     04  RTC hours
     05  RTC hours alarm
     06  RTC day of week
     07  RTC day of month
     08  RTC month
     09  RTC year
     0A  RTC Status register A:

        │7│6│5│4│3│2│1│0│  RTC Status Register A
         │ │ │ │ └─┴─┴─┴──── rate selection Bits for divider output
         │ │ │ │         frequency (set to 0110 = 1.024kHz, 976.562µs)
         │ └─┴─┴────────── 22 stage divider, time base being used;
         │              (initialized to 010 = 32.768kHz)
         └────────────── 1=time update in progress, 0=time/date available

     0B  RTC Status register B:

        │7│6│5│4│3│2│1│0│  RTC Status Register B
         │ │ │ │ │ │ │ └──── 1=enable daylight savings, 0=disable (default)
         │ │ │ │ │ │ └───── 1=24 hour mode, 0=12 hour mode (24 default)
         │ │ │ │ │ └────── 1=time/date in binary, 0=BCD (BCD default)
         │ │ │ │ └─────── 1=enable square wave frequency, 0=disable
         │ │ │ └──────── 1=enable update ended interrupt, 0=disable
         │ │ └───────── 1=enable alarm interrupt, 0=disable
         │ └────────── 1=enable periodic interrupt, 0=disable
         └─────────── 1=disable clock update, 0=update count normally

     0C  RTC Status register C (read only):

        │7│6│5│4│3│2│1│0│  RTC Status Register C  (read only)
         │ │ │ │ └─┴─┴─┴──── reserved (set to 0)
         │ │ │ └────────── update ended interrupt enabled
         │ │ └────────── alarm interrupt enabled
         │ └────────── periodic interrupt enabled
         └────────── IRQF flag

     0D  RTC Status register D (read only):

        │7│6-0│  RTC Status Register D  (read only)
         │    └───── reserved (set to 0)
         └────── 1=CMOS RAM has power, 0=CMOS RAM has lost power

     0E  Diagnostic status byte:

        │7│6│5│4│3│2│1│0│  Diagnostic Status Byte
         │ │ │ │ │ │ └─┴──── reserved
         │ │ │ │ │ └─────── 1=time is invalid, 0=ok (POST validity check)
         │ │ │ │ └──────── 1=fixed disk 0 failed initialization, 0=ok
         │ │ │ └───────── 1=memory size doesn't match config info, 0=ok
         │ │ └────────── 1=invalid config info found, 0=ok (see below)
         │ └─────────── 1=config record checksum is bad, 0=ok
         └──────────── 1=RTC lost power, 0=power state stable

     0F  Shutdown status byte:

           0  soft reset or unexpected shutdown
           1  shut down after memory size determination
           2  shut down after memory test
           3  shut down with memory error
           4  shut down with boot loader request
           5  JMP DWORD request with INT init
           6  protected mode test 7 passed
           7  protected mode test 7 failed
           8  protected mode test1 failed
           9  block move shutdown request
           A  JMP DWORD request without INT init

     10  Diskette drive type for A: and B:

        │7│6│5│4│3│2│1│0│  Diskette drive type for A: and B:
         │ │ │ │ └─┴─┴─┴──── second diskette type
         └─┴─┴─┴─────────── first diskette type

        0000  no drive installed
        0001  DSDD 48 TPI drive
        0010  DSQD 96 TPI drive
        other values are reserved

     11  Reserved
     12  Fixed disk drive type for drive 0 and drive 1

        │7│6│5│4│3│2│1│0│  Diskette drive type for A: and B:
         │ │ │ │ └─┴─┴─┴──── second hard disk drive code (0000=no disk)
         └─┴─┴─┴─────────── first hard disk drive code (0000=no disk)

     13  Reserved
     14  Equipment byte

        │7│6│5│4│3│2│1│0│  Equipment byte
         │ │ │ │ │ │ │ └──── 1=diskette drives installed, 0=none
         │ │ │ │ │ │ └───── 1=math coprocessor installed, 0=none
         │ │ │ │ └─┴────── unused
         │ │ └─┴─────── primary display
         └─┴────────── number of diskette drives installed

%        Bits               Bits
%         54  Primary Display    76  Number of Drives
         00  reserved        00  1 diskette drive
         01  40 column color    01  2 diskette drives
         10  80 column color    10  reserved
         11  monochrome        11  reserved

     15  LSB of system base memory in 1k blocks
     16  MSB of system base memory in 1k blocks
     17  LSB of total extended memory in 1k blocks
     18  MSB of total extended memory in 1k blocks
     19  Drive C extension byte (reserved AT)
     1A  Drive D extension byte (reserved AT)
     1B  13 bytes reserved
     2E  CMOS checksum of bytes 10h-20h (MSB)
     2F  CMOS checksum of bytes 10h-20h (LSB)
     30  LSB of extended memory size found above 1 megabyte during POST
     31  MSB of extended memory size found above 1 megabyte during POST
     32  Date century byte in BCD ( BIOS interface to read and set)
     33  Information flags (set during power-on)

        │7│6│5-0│  Information Flags
         │ │  └───── reserved
         │ └─────── initial setup message flag
         └──────── 1=IBM 128k expansion installed, 0=none

     34  12 bytes reserved


%    Programming Considerations:

    Write CMOS address to read or write to port 70h
    Read/write port 71h to get/set data


    - the information here is only applicable to AT and PS/2 systems
    - INT 1A is used to read/set the Time of Day and Alarm.  To use the
      alarm, INT 4A must be a valid interrupt service routine.
    - configuration settings are maintained using the Motorola MC146818
      Real Time Clock.  Each of this chips 64 memory registers is used
      for storage (0-3F).
    - Bit 5 of the diagnostic (0Eh) status byte is set during a power
      on test.  This Bit is set if no floppy disks are found or the
      display doesn't match the system display switch setting.
    - all addresses sent to port 70h have Bits 7&6 clear since Bit 7
      of port 70h is used to enable/disable NMI.  Setting this Bit 7
      enables NMI, clearing this Bit disables NMI.
    - when masking the NMI through using port 70H, port 71H should be
      read immediately after or the RTC may be left in an unknown state.
      This wont affect the PS/2 watchdog timer or system channel timeout.

    - see    ~INT 1A~
:Epson printer codes
^Epson FX Printer Codes

%    Printer Operation:
%    Decimal      ASCII            Description
     7         BEL      Beeper
    17         DC1      Select printer
    19         DC3      Deselect printer
    27 25 48     ESC EM 0      Turn cut sheet feeder control off
    27 25 52     ESC EM 4      Turn cut sheet feeder control on
    27 56         ESC 8      Disable paper out sensor
    27 57         ESC 9      Enable paper out sensor
    27 60         ESC <      Select unidirectional mode for one line
    27 64         ESC @      Initialize printer
    27 85 48     ESC U 0      Cancel unidirectional mode
    27 85 49     ESC U 1      Select unidirectional mode
    27 115 48    ESC s 0      Turn half speed mode off
    27 115 49    ESC s 1      Turn half speed mode on

%    Vertical/Horizontal Motion:
%    Decimal      ASCII            Description
     8         BS       Backspace
     9         HT       Horizontal tab
    10         LF       Line Feed
    11         VT       Vertical Tab
    12         FF       Form Feed
    27 47 c      ESC / c      Select vertical tab channel (c=0..7)
    27 48         ESC 0      Select 8 lines per inch
    27 49         ESC 1      Select 7/72 inch line spacing
    27 50         ESC 2      Select 6 lines per inch
    27 51 n      ESC 3 n      Select n/216 inch line spacing (n=0..255)
    27 65 n      ESC A n      Select n/72 inch line spacing (n=0..85)
    27 66 0      ESC B NUL      Clear Vertical tabs
    27 66 tabs   ESC B tabs   Select up to 16 vertical tabs where tabs are
                  ascending values from 1..255 ending with NUL
    27 67 n      ESC C n      Select page length in lines (n=1..127)
    27 67 48 n   ESC C 0 n      Select page length in inches (n=1..22)
    27 68 0      ESC D NUL      Clears all horizontal tables
    27 68 tabs 0 ESC D tabs NUL  Sets up to 32 horizontal tabs with
                  ascending values 1-137.  NUL or a value
                  less than previous tab ends command.
    27 74 n      ESC J n      Immediate n/216 inch line feed (n=0..255)
    27 78 n      ESC N n      Select skip over perforation (n=1..127)
    27 79         ESC O      Cancel skip over perforation
    27 81 n      ESC Q n      Set right margin (n=column)
    27 98 b c 0  ESC b c NUL  Clear vertical tabs in channel (c=0..7)
    27 98 c tabs ESC b c tabs Select up to 16 vertical tabs in channels
                  (c=0..7) where tabs are ascending values
                  from 1..255 ending with NUL
    27 101 48 s  ESC e 0 s      Set horizontal tab to increments of 's'
    27 101 49 s  ESC e 1 s      Set vertical tab to increments of 's'
    27 102 48 s  ESC f 0 s      Set horizontal skip to increments of 's'
    27 102 49 s  ESC f 1 s      Set vertical skip to increments of 's'
    27 106 n     ESC j n      Reverse linefeed (n/216 inch after buffer)
    27 108 n     ESC l n      Set left margin (n=column)

%    Printing Style:
%    Decimal      ASCII            Description
    27 33 n      ESC ! n      Master select where n is a combination of:
                    0  Pica         16  Double Strike
                    1  Elite         32  Double Wide
                    4  Condensed     64  Italic
                    8  Emphasized    128  Underline
                  Pica & Elite and Condensed/Emphasized are
                  mutually exclusive
    27 107 48    ESC k 0      Select NLQ Roman font
    27 107 49    ESC k 1      Select NLQ Sans Serif font
    27 120 48    ESC x 0      Select draft mode
    27 120 49    ESC x 1      Select NLQ mode

%    Print Size and Character Width:
%    Decimal     ASCII           Description
    14        SO          Select double width for one line
    15        SI          Select condensed mode
    18        DC2       Cancel condensed mode
    20        DC4       Cancel one line double width mode
    27 14        ESC SO      Double width for one line (duplicate)
    27 15        ESC SI      Select condensed mode (duplicate)
    27 77        ESC M      Select elite width (12 cpi)
    27 80        ESC P      Select pica width (10 cpi)
    27 87 48    ESC W 0      Cancel double width mode
    27 87 49    ESC W 1      Select double width mode

%    Print Enhancement:
%    Decimal     ASCII           Description
    27 45 48    ESC - 0      Cancel underlining
    27 45 49    ESC - 1      Select underlining
    27 69        ESC E      Select emphasized mode
    27 70        ESC F      Cancel emphasized mode
    27 71        ESC G      Select double strike mode
    27 72        ESC H      Cancel double strike mode
    27 83 48    ESC S 0      Select superscript
    27 83 49    ESC S 1      Select subscript
    27 84        ESC T      Cancel superscript/subscript

%    Character Sets:
%    Decimal     ASCII           Description
    27 52        ESC 4      Select italic mode
    27 53        ESC 5      Cancel italic mode
    27 54        ESC 6      Enable printing of characters (128-159,255)
    27 55        ESC 7      Cancel [ESC 6] command
    27 82 n     ESC R n      Select International character set where
                  numeric 'n' is:
                    0  USA          7  Spain I
                    1  France          8  Japan
                    2  Germany          9  Norway
                    3  United Kingdom     10  Denmark II
                    4  Denmark I     11  Spain II
                    5  Sweden         12  Latin America
                    6  Italy
    27 116 0    ESC t NUL     Select italic character set
    27 116 1    ESC t SOH     Select Epson character set

%    User Defined Characters:
%    Decimal        ASCII            Description
    27 37 0      ESC % NUL        Selects normal character set
    27 37 1      ESC % SOH        Selects user defined set
    27 38 0      ESC & NUL ?    Select user defined chars (see manual)
    27 58 0 0 0  ESC : NUL NUL NUL    Copy ROM into RAM

%    Graphics Character Sets:
%    Decimal        ASCII            Description
    27 42 0 n1 n2  ESC * NUL n1 n2    Select single density graphics
    27 42 1 n1 n2  ESC * SOH n1 n2    Select double density graphics
    27 63 s n      ESC ? s n    Reassign graphics mode
                    's'=(K,L,Y or Z) to mode 'n'=(0..6)
    27 75 n1 n2    ESC K n1 n2    Single density graphics (60 dpi)
    27 76 n1 n2    ESC L n1 n2    Double density graphics (120 dpi)
    27 89 n1 n2    ESC Y n1 n2    Hi-speed double den graphics (120 dpi)
    27 90 n1 n2    ESC Z n1 n2    Quad density graphics (240 dpi)
    27 94 m n1 n2  ESC ^ m n1 n2    Select 9 pin graphics mode

    number of columns = n1 + (n2 * 256)

%    Other:
%    Decimal      ASCII            Description
     13         CR       Carriage Return
     24         CAN      Cancel text in line (but not control codes)
    127         DEL      Delete character (but not control codes)
     27 32 n     ESC SP n      Space in n/72 inch following each NLQ char
     27 35         ESC #      MSB control sequence cancel
     27 36         ESC $      Select absolute dot position
     27 61         ESC =      MSB = 0
     27 62         ESC >      MSB = 1
     27 73 48    ESC I 0      Cancel above [ESC I 1]
     27 73 49    ESC I 1      Printable codes expansion (0-31,128-159)
     27 92         ESC \      Select relative dot position
     27 97    n    ESC a n      NLQ justification where numeric 'n' is:
                    0  left justification  (default)
                    1  center
                    2  right justification
                    3  full justification
     27 112      ESC p      Select/cancel proportional mode


    - the codes listed are relative to the Epson LX 800
    - in several situations where a numeric value of zero or one is
      required, the ASCII value of the number can be substituted
:hard disks drives:drive specifications:disk drives:hard drives
^Hard Drive Specifications

%                        Avg          Miscellaneous
%   Manufacturer        MB    Cyl  Hds Access      Information

    Alloy ID-160       125             30
    Atasi AT3020          635   3      Wedge servo
    Atasi AT3033          635   5      Wedge servo
    Atasi AT3046          635   7
    Atasi AT3051          703   7
    Atasi AT3085         1024   8
    Bull D530                  987   3
    Bull D550                  987   5
    Bull D570                  987   7
    Bull D585                  987   7
    Bull D530                1166   3
    CDC Wren I 9415-21              697   3      STnn, MFM, Voice coil
    CDC Wren I 9415-36              697   5      STnn, MFM, Voice coil
    CDC Wren II 9415-25              615   4      STnn, MFM, Voice coil
    CDC Wren II 9415-30              989   3      STnn, MFM, Voice coil
    CDC Wren II 9415-38              733   5      STnn, MFM, Voice coil
    CDC Wren II 9415-48              925   5      STnn, MFM, Voice coil
    CDC Wren II 9415-51     42    989   5    28      STnn, MFM, Voice coil
    CDC Wren II 9415-67              925   7      STnn, MFM, Voice coil
    CDC Wren II 9415-86     69    925   9      STnn, MFM, Voice coil
    CDC Wren II 9416-182   144    969   9      STnn, MFM, Voice coil
    CDC Wren V                   380  15    16   ESDI/SCSI, FH
    CDC Wren V                   702  15    16   ESDI/SCSI, FH
    CDC Wren VI                   766  15   16.5  ESDI/SCSI, FH
    CDC Wren VII      1.2G           15   16.5  SCSI, FH
    CMI CM3426                  612   4
    CMI CM5205                  256   4
    CMI CM5410                  256   4
    CMI CM5616                  256   4
    CMI CM6426                  615   4
    CMI CM6426S                  640   4
    CMI CM6640                   640   4
    CMS F40-K                  42   1024   5    22      STnn, MFM, Voice coil
    CMS F60-K                  42   1024   7      STnn, MFM, Voice coil
    CMS F70-K                  42   1024   8      STnn, MFM, Voice coil
    CMS F80-K                  42   1024   9      STnn, MFM, Voice coil
    Columbia SCSI        42    834   3    19   SCSI, RLL, Band stepper
    Core AT40F                  40    564   4    10   ESDI, MFM, Voice coil
    Core AT43                  43    988   5    20   STnn, MFM, Voice coil
    Core HC150                150   1024+       18   ESDI
    Emerald DOS 150-3000   150   1024+              ESDI
    Emulex ATS-170       142   1022               SCSI & ESDI
    Emulex ATS-380       310   1222               SCSI & ESDI
    FlashCard 49        49    615   6    28   STnn, RLL, Voice coil
    Fuji 302-13                  10    612   2
    Fuji 302-26                  20    612   4
    Fujitsu M2230AS           320   2
    Fujitsu M2233AS         10    320   4
    Fujitsu M2234AS           320   6
    Fujitsu M2235AS         21    320   8    56
    Fujitsu M2241AS               754   4
    Fujitsu M2242AS         43    754   7    33   STnn, MFM, Voice coil
    Fujitsu M2243AS         72    754  11    33   STnn, MFM, Voice coil
    Fujitsu M2263       778u           14    16   ESDI/SCSI, FH
    Hitachi DK511-5        699            7
    Hitachi DK511-8        823         10
    Hitachi DK515C-78      780u            8    16   SCSI, FH
    Hitachi DK515-78       780u            8    16   ESDI, FH
    IMI 5006H                 306   2
    IMI 5012H                 306   4
    IMI 5018H              306   6
    Imprimis (see CDC)
    Irwin 416                 819   2
    Irwin 510                 628   2      HD/tape
    Irwin 516                 819   2      HD/tape
    Irwin 561              180   4
    Kalok KL320                  26u   615   4    40   STnn, MFM, Band stepper
    Kalok KL330                  38u   615   4    40   STnn, RLL, Band stepper
    Maxtor XT1065        52    918   7    28   STnn, Voice coil
    Maxtor XT1085        68   1024   8    28   STnn, Voice coil
    Maxtor XT1105        83    918  11    28   STnn, Voice coil
    Maxtor XT1140       112    918  15    28   STnn, Voice coil
    Maxtor XT1190       150   1224        28   STnn, Voice coil
    Maxtor XT2085         1224   7    28   STnn, Voice coil
    Maxtor XT2140         1224  11      STnn, Voice coil
    Maxtor XT2190       160   1224  15      STnn, Voice coil
    Maxtor XT4170E       179u  1224   7    14   ESDI, MFM, FH Voice coil
    Maxtor XT4230E       231u  1224   9    16   ESDI, MFM, FH Voice coil
    Maxtor XT4380E       384u  1224  15    16   ESDI, MFM, FH Voice coil
    Maxtor XT4380S       384u  1224        16   SCSI, MFM, FH Voice coil
    Maxtor XT8380E       410u                14.5  ESDI, FH
    Maxtor XT8380S       410u                14.5  SCSI, FH
    Maxtor XT8760E       768u                16.5  ESDI, FH
    Maxtor XT8760S       768u                16.5  SCSI, FH
    Micropolis 1302              830   3
    Micropolis 1303              830   5
    Micropolis 1304              830   6
    Micropolis 1323            1024   4
    Micropolis 1323A           1024   5
    Micropolis 1324            1024   6
    Micropolis 1324A           1024   7
    Micropolis 1325            1024   8
    Micropolis 1333A        44   1024   5    28   STnn, MFM, Voice coil
    Micropolis 1335         71   1024   8    30
    Micropolis 1355        142   1022
    Micropolis 1518       1.2Gu        15    14   ESDI, FH
    Micropolis 1558        382u           15    18   ESDI, FH
    Micropolis 1568        765u           15    16   ESDI, FH
    Micropolis 1578        382u           15    18   SCSI, FH
    Micropolis 1588        765u           15    16   SCSI, FH
    Micropolis 1598       1.2Gu           15    14   SCSI, FH
    Microscience HH312      10    306   4
    Microscience HH325      20    612   4
    Microscience HH612      10    306   4
    Microscience HH725      21    612   4      Band stepper
    Microscience HH1050     44   1024   5    28   STnn, MFM, Voice coil
    Miniscribe 1006               306   2
    Miniscribe 1012              306   4
    Miniscribe 2006               306   2
    Miniscribe 3012         10    612   4
    Miniscribe 3053         44   1024   6    25   STnn, MFM, Voice coil
    Miniscribe 3212         10    612   4
    Miniscribe 3412           306   4
    Miniscribe 3425         20    615   4
    Miniscribe 3438       31.2    615   4
    Miniscribe 3650         50u   809   6    61   STnn, MFM, linear drive
    Miniscribe 3650F        50u   809   6    46   STnn, MFM, linear drive
    Miniscribe 3675         75u   809   6    61   STnn, MFM, linear drive
    Miniscribe 4010               480   2
    Miniscribe 4020               480   4
    Miniscribe 6032         26   1024   3
    Miniscribe 6053         43   1024   5    28   STnn, MFM, FH Voice coil
    Miniscribe 6085         71   1024   8
    Miniscribe 6128        104   1024   8
    Miniscribe 8051A        51u   745   4    28   STnn, MFM, Voice coil
    Miniscribe 8212           615   2
    Miniscribe 8425         20    615   4      STnn, MFM, 3½
    Miniscribe 8438       31.2    615   4
    Miniscribe 9380E       382u  1224  15    16   ESDI, RLL, FH Voice coil
    Miniscribe 9380S       382u  1224  15    16   SCSI, RLL, FH Voice coil
    Miniscribe 9780E       781u           15    17   ESDI, FH Voice coil
    Mitsubisi MR535         42    981   6      STnn, MFM, 5¼ Voice coil
    NEC D5662                385u                 18   ESDI, FH
    NEC D5682               765u           18    16   ESDI, FH
    NEC D5862               385u                 18   SCSI, FH
    NEC D5882               765u           18    16   SCSI, FH
    NEC 5124              310   4
    NEC 5126              612   4
    NEC 5146              615   8
    Newberry Penny 340             615   8
    Northgate Turbo         42    809   6    36   STnn, RLL, Voice coil
    Plus Hardcard 40        42    612   4    40   STnn, RLL, Voice coil
    Priam ID45ATD2        42   1166   5    20   STnn, MFM, Voice coil
    Priam ID130                130   1224            STnn
    Priam ID40                 987   5
    Priam ID60              987   7
    Priam V130               987   3      STnn
    Priam V185               1166   7
    Priam 638                382u           15    18   ESDI, 5¼
    Priam 676                765u           15    14   ESDI, 5¼
    Priam 738                382u           15    18   SCSI, 5¼
    Priam 776                765u           15    14   SCSI, 5¼
    Quadram Q520          512   4
    Quadram Q530          512   6
    Quadram Q540          512   8
    Rodime RO101          192   2
    Rodime RO102          192   4
    Rodime RO103          192   6
    Rodime RO104          192   8
    Rodime RO201          320   2
    Rodime RO202          320   4
    Rodime RO203          320   6
    Rodime RO204          320   8
    Rodime RO201E          640   2
    Rodime RO202E          640   4
    Rodime RO203E        33    640   6
    Rodime RO204E          640   8
    Rodime RO252        10    306   4
    Rodime RO352        10    306   4
    Rodime RO3055        45    872   7      STnn, MFM, Voice coil
    RMS 503                  153   2
    RMS 506               153   4
    RMS 512               153   8
    Seagate ST125        21    615   4    28   STnn, MFM, Band stepper
    Seagate ST125N        22    407   4           SCSI, RLL, Band stepper
    Seagate ST138        32    615   6    28   STnn, MFM, 3½ Band stepper
    Seagate ST138N        31    615   4    28   SCSI, RLL, Band stepper
    Seagate ST138R        33    615   4    28   STnn, RLL, Band stepper
    Seagate ST151        43    977   5      STnn, MFM, Voice Coil
    Seagate ST157A        49    560   6    28   IDE, 3½
    Seagate ST157N        49    615   6    28   SCSI, 3½ RLL, Band stepper
    Seagate ST157R        49    615   6    28   STnn, 3½ RLL, Voice Coil
    Seagate ST177N        61    921   5      SCSI, RLL, Voice Coil
    Seagate ST206              306   2      STnn, MFM, Band stepper
    Seagate ST213        11    615   2      STnn, MFM, Band stepper
    Seagate ST225        21    615   4    65   STnn, MFM, 5¼ Band stepper
    Seagate ST225N        21    615   4    65   SCSI, MFM, 5¼ Band stepper
    Seagate ST225R        21    667   2      STnn, RLL, 5¼ Band stepper
    Seagate ST238R        31    615   4    65   STnn, RLL, Band Stepper
    Seagate ST250R        42    667   4      STnn, RLL, Band stepper
    Seagate ST251        42    820   6    40   STnn, MFM, 5¼ Band stepper
    Seagate ST251-1         43    820   6    28   STnn, MFM, 5¼ Band stepper
    Seagate ST251N0         43    820   4    40   SCSI, RLL, 5¼ Band stepper
    Seagate ST251N1         43    630   4      SCSI, RLL, 5¼ Band stepper
    Seagate ST251R        43    820   6    40   STnn, RLL, 5¼ Band stepper
    Seagate ST277        66    820   6      STnn, MFM, 5¼ Band stepper
    Seagate ST277N0         65    820   6    40   SCSI, RLL, 5¼ Band stepper
    Seagate ST277N1         65    628   6      SCSI, RLL, 5¼ Band stepper
    Seagate ST277R        65    820   6    40   STnn, RLL, 5¼ Band stepper
    Seagate ST280A        72                 29   IDE, 5¼
    Seagate ST296N        85    820   6    28   SCSI, RLL, 5¼ Band stepper
    Seagate ST406         5    306   2      STnn, MFM, Band stepper
    Seagate ST412        10    306   4      STnn, MFM, FH Band stepper
    Seagate ST419        15    306   6      STnn, MFM, Band stepper
    Seagate ST425        20    306   8      STnn, MFM, Band stepper
    Seagate ST506         5    153   4      STnn, MFM, FH Band stepper
    Seagate ST1096N         84    906   7      SCSI, RLL, Voice coil
    Seagate ST1102A         89                 29   IDE, 3½
    Seagate ST1144       125                 19   IDE, 3½
    Seagate ST1239       211                 15   IDE, 3½
    Seagate ST4026        21    615   4      STnn, MFM, Voice coil
    Seagate ST4038        32    733   5    40   STnn, MFM, FH Voice coil
    Seagate ST4051        43    977   5    40   STnn, MFM, Voice coil
    Seagate ST4053        44   1024   5    28   STnn, MFM, Voice coil
    Seagate ST4077R         65   1024   5    28   STnn, MFM, Voice coil
    Seagate ST4096        80   1024   9    28   STnn, MFM, FH Voice coil
    Seagate ST4144R        122   1024   9    28   STnn, RLL, FH Voice coil
    Shugart SA 604              160   4
    Shugart SA 606          160   6
    Shugart SA 612          306   4
    Shugart SA 712          320   4
    SPC Scorecard 44        44    753   7      STnn, MFM, Voice coil
    Syquest SQ306RD              306   2
    Syquest SQ312RD              615   2
    Syquest SQ325F          612   4
    Syquest SQ338F          612   6
    Tandon TM252        10    306   4
    Tandon TM262        20    615   4
    Tandon TAN501          306   2
    Tandon TAN502          306   4
    Tandon TAN503          306   6
    Tandon TM602S          153   4
    Tandon TM603S          153   6
    Tandon TM603SE          230   6
    Tandon TM702AT          615   4
    Tandon TM703          695   5
    Tandon TM703AT          733   5
    Tandon TM755          981   5
    Tandy SCSI                  80    823   6    28   SCSI, RLL, Band stepper
    Toshiba MK53F          830   5
    Toshiba MK54F        49    830   7    25   STnn, MFM, 3½ Voice coil
    Toshiba MK56F        72    830  10    25
    Toshiba MK134FA               733   7    25   STnn
    Toshiba MK358FA        765u           15    16   ESDI, FH
    Toshiba MK358FB        765u           15    16   SCSI, FH
    Tulin 226                 640   4
    Tulin 240                  640   6
    Tulin 326                  20    640   4
    Tulin 340                  30    640   6
    WD93024A              21.6                 28   STnn, MFM, 3½ Band stepper
    WD93024X               21.6                 39   STnn, MFM, 3½ Band stepper
    WD93028A               21.6                 69   STnn, MFM, 3½ Band stepper
    WD93028X               21.6                 70   STnn, MFM, 3½ Band stepper
    WD93034X               32.4                 39   STnn, MFM, 3½ Band stepper
    WD93038X                 32.4                 70   STnn, MFM, 3½ Band stepper
    WD93044A               43.2                 28   STnn, MFM, 3½ Band stepper
    WD93044X               43.2                 39   STnn, MFM, 3½ Band stepper
    WD93048A               43.2                 69   STnn, MFM, 3½ Band stepper
    WD93048X               43.2                 70   STnn, MFM, 3½ Band stepper
    WD95024A                 20                  28   STnn, MFM, 5¼ Band stepper
    WD95028AD                 20                  69   STnn, MFM, 5¼ Band stepper
    WD95028X                 20                  70   STnn, MFM, 5¼ Band stepper
    WD95038X                 30                  70   STnn, MFM, 5¼ Band stepper
    WD95044A                 40                  28   STnn, MFM, 5¼ Band stepper
    WD95048AD                 40                  69   STnn, MFM, 5¼ Band stepper
    WD95048X                 40                  70   STnn, MFM, 5¼ Band stepper
    WDAC140                42.5                 19   STnn, MFM, 3½ Voice coil
    WDAC280                85.1                 19   STnn, MFM, 3½ Voice coil
    WDSC320                 320                       SCSI, 3½
    WDSC8320                320                       SCSI, 3½


    - STnn indicates Seagate ST412/ST506 compatible
    - 3½ indicates 3.5 inch half height drive
    - 5¼ indicates 5.25 inch half height drive
    - FH indicates Full Height 5.25 inch drive
    - 'u' in filesize indicates unformatted spec
    - formatted capacity is related to BIOS and may vary with different
      BIOS and OEM versions
    - read/write heads should normally never touch hard disk media
    - standard AT hard disk controllers do not use DMA for disk I/O due
      to the slow speed of the 8 Bit DMA chips used;  Port I/O is used
      instead for an actual increase in performance
    - with some XT and ESDI systems it is necessary to use debug to
      execute the ROM disk format code;  The usual method is to set
      AH=Drive, AL=Interleave and jump to the code at C800:5 via the
      G =C800:5 command (some systems locate this code at C600:5, CA00:5
      and CC00:5)
    - DOS version and disk size determine cluster size;   DOS 2.x always
      has cluster size of 8K, while DOS 3.x+ has variable cluster sizes:

            2 - 16  Mb partitions have a cluster size of 8K
           16 - 128 Mb partitions have a cluster size of 2K
          128 - 256 Mb partitions have a cluster size of 4K
          256 - 512 Mb partitions have a cluster size of 8K

:Hayes modem info:modem commands
^Hayes Command Set / Register Formats

    +++    standard escape sequence (see S2 below)
    Comma  standard pause character (see S8 below)
    AT     standard attention sequence

    ATA    force immediate answer
    ATC0   transmitter off
    ATC1   transmitter on

    ATD    dial (ATD number)
    ATDP   pulse dial (ATDP number)
    ATDT   tone dial (ATDT number)

    ATE0   disable local character echo
    ATE1   enable local character echo
    ATF0   Half Duplex (modem echoes characters)
    ATF1   Full Duplex (modem does not echo characters)

    ATH0   force line on hook
    ATH1   force line off hook
    ATH2   force line special off hook (used for HAM radio)

    ATI0   request product code, formatted PPR, PP=prod., R=rev.
    ATI1   request ROM check sum

    ATL1   speaker volume low  (modem specific)
    ATL2   speaker volume medium  (modem specific)
    ATL3   speaker volume high  (modem specific)
    ATM0   speaker always off
    ATM1   speaker on except while carrier present
    ATM2   speaker always on
    ATM3   speaker on except while dialing and carrier present

    ATO    force modem into on-line state
    ATP    sets modem to default pulse dial

    ATQ0   modem returns result codes
    ATQ1   modem does not return result codes

    ATR    sets modem to answer mode after dialing out
    ATSn   where Sn is S register number 'n' (see registers below)
    ATT    sets modem to default tone dial

    ATV0   send numeric codes
    ATV1   send word result codes

    ATX0   basic result code set "CONNECT", no dial tone detect
    ATX1   extended result code set "CONNECT 1200", no dialtone detect
    ATX2   wait for dial tone, extended result codes
    ATX3   detect busy signal, extended result codes
    ATX4   wait for dial tone, detect busy, extended result codes

    ATZ    reset to power up condition

^Hayes 2400 Compatible Modem Commands

    ATB0    CCITT V.22 at 1200 bps
    ATB1    BELL 212A at 1200 bps

    AT&C    DCD always on
    AT&C1    DCD on while carrier present

    AT&D    DTR ignored
    AT&D1    DTR fail disconnect enabled
    AT&D2    DTR fail disconnect enabled (auto answer off)
    AT&D3    DTR fail disconnect enabled (reset modem)

    AT&F    restore to factory configuration

    AT&G    no guard tone
    AT&G1    550 Hz guard tone
    AT&G2    1800 Hz guard tone

    AT&J    RJ11/RJ41S/RJ45 jack
    AT&J2    RJ12/RJ13 jack

    AT&L    regular phone line
    AT&L1    leased line

    AT&M    async operation
    AT&M1    async/sync operation
    AT&M2    sync auto dial
    AT&M3    sync manual dial

    AT&P    39/61 pulse make/break ratio
    AT&P1    33/67 pulse make/break ratio

    AT&T4    grant RDL test request
    AT&T5    deny RDL test request

    AT&W    write current registers to non-volatile memory

    AT&X    sync clock internal

    AT&X1    sync clock external
    AT&X2    sync clock slaved

    AT&Z    store dial command line

^Hayes Compatible Modem Registers

    Not all modems support all of these registers and some modems have
    registers other than those listed here.  Also note, some are read only.

    to set a register use:        AT Sr=##  (cr)
    to read the register:        AT Sr?     (cr)

    Where "r" is the register and (cr) is a carriage return


%    The following represent conventions used in the tables below:

    () indicates defaults for Smartmodem 1200
    ** indicates possible inconsistencies across modems


%    Reg  Values       Register function

    S0   0-255    ring to answer on (0=don't answer)
    S1   0-255    ring count (clear after 8 sec) (read only)
    S2   0-255    escape char, normally "+", 128-255 disable escape
    S3   0-127    end of line character (0x0D/CR)
    S4   0-127    line feed character (0x0A/LF)
    S5   0-32,127 backspace character (0x08/BS)
    S6   2-255    pause before dialing in seconds (2)
    S7   1-255    wait for carrier in seconds (30)
    S8   0-255    pause for comma in dial string in seconds (2)
    S9   1-255    carrier detect response time in 1/10 second (6)
    S10  1-255    carrier loss delay in 1/10 second, 255=ignore CD (7)
    S11 50-255    touch tone dial speed, in milliseconds (70)
    S12 20-255    escape guard time, in 1/50 second,0=no delay (50)

    │7│6│5│4│3│2│1│0│  S13     power up async data format
     │ │ │ │ │ │ │ └──── unused
     │ │ │ │ │ │ └───── result code, 0=basic, 1=extended
     │ │ │ │ │ └────── parity, 0=disabled, 1=enabled
     │ │ │ │ └─────── parity, 0=odd ,1=even
     │ │ │ └──────── data bits, 0=7 bits, 1=8 bits
     │ │ └───────── undefined
     │ └────────── buffer ovfw flag, 0=disabled,1=enabled
     └─────────── 8th bit, 0=space,1=mark (8 bit only)

    │7│6│5│4│3│2│1│0│  S14     option register status data format
     │ │ │ │ │ │ │ └──── unused **
     │ │ │ │ │ │ └───── local echo, 0=disabled, 1=enabled
     │ │ │ │ │ └────── result codes, 0=enabled,1=disabled
     │ │ │ │ └─────── result codes, 0=numeric,1=word
     │ │ │ └──────── command recognition, 0=enable,1=disable
     │ │ └───────── dial method, 0=touch tone, 1=pulse
     │ └────────── unused **
     └─────────── 0=answer, 1=originate **

    S15          flag register **

    │7│6│5│4│3│2│1│0│  S16     test status
     │ │ │ │ │ │ │ └──── analog loop, 0=inactive, 1=active
     │ │ │ │ │ │ └───── unused
     │ │ │ │ │ └────── digital loop, 0=inactive, 1=active
     │ │ │ │ └─────── remote req digital loop,0=inact.,1=active
     │ │ │ └──────── remote digital loop,0=inact.,1=active
     │ │ └───────── self test RDL, 0=inactive, 1=active
     │ └────────── self test analog loop,0=inactive,1=active
     └─────────── unused

    S18 0-255     remote test timer in seconds

    │7│6│5│4│3│2│1│0│  S21     option status
     │ │ │ │ │ │ │ └──── jack type, 0=RJ11,RJ41,RJ45,1=RJ12,RJ13
     │ │ │ │ │ │ └───── unused
     │ │ │ │ │ └────── CTS state,  0=follows RTS, 1=forced on
     │ │ │ └─┴─────── DTR modem behavior (see below)
     │ │ └────────── DCD, 0=forced on, 1=follows carrier
     │ └─────────── DSR, 0=forced on, 1=behaves normally
     └──────────── long space disconnect,0=disabled,1=enabled

%    Bits
%     43  DTR Modem Behavior Bits
     00  ignore DTR
     01  assume command state when DTR drops
     10  assume command state and disable auto-answer when DTR drops
     11  reset when DTR drops


    │7│6│5│4│3│2│1│0│  S22     option status
     │ │ │ │ │ │ └─┴──── speaker volume, 01=low,10=med,11=high
     │ │ │ │ └─┴─────── speaker setting (see below)
     │ └─┴─┴────────── X command in effect
     └─────────────── make/break ratio, 0=39/61, 1=33/67

%    Bits
%     32  S22 Speaker Setting
     00  speaker always off
     01  speaker on until carrier detected
     10  speaker always on
     11  speaker off during dialing, then on until CD

%    Bits
%    654  S22 X Command in Effect
    100  X1 command in effect
    101  X2 command in effect
    110  X3 command in effect
    111  X4 command in effect


    │7│6│5│4│3│2│1│0│  S23     option status
     │ │ │ │ │ │ │ └──── remote dig.loop request,0=denied,1=ok
     │ │ │ │ │ └─┴───── baud rate (see table)
     │ │ │ │ └──────── unused
     │ │ └─┴───────── parity (see table)
     └─┴──────────── guard tone setting

%    Bits
%     21  S23 Baud Rate Table
     00  0-300 bps
     01  600 bps
     10  1200 bps
     11  2400 bps

%    Bits
%     54  S23 Parity Setting
     00  even parity
     01  parity bit always 0
     10  odd parity
     11  parity bit always 1

%    Bits
%     76  S23 Guard Tone Setting
     00  no guard tones
     01  550 hz guard tone
     10  1800 hz guard tone

    S25 0-255     DTR detect delay in seconds (5)
    S26 0-255     RTS to CTS delay in milliseconds (1)

    │7│6│5│4│3│2│1│0│  S27     option status
     │ │ │ │ │ │ └─┴──── synch/async mode (see table)
     │ │ │ │ │ └─────── phone line, 0= public, 1=leased
     │ │ │ │ └──────── unused
     │ │ └─┴───────── clock type (see table)
     │ └──────────── protocol, 0=CCITT V.22, 1=Bell 212A
     └───────────── unused

%    Bits
%     10  S27 Sync/Async mode
     00  asynchronous mode
     01  async/sync mode
     10  sync auto-dial
     11  sync manual dial

%    Bits
%     45  S27 Clock Type
     00  internal clock used
     01  external clock used
     10  slaved clock used
:game port:joystick
^Joystick / Game Port (201h)

    │7│6│5│4│3│2│1│0│  Port at 201h used with Joysticks
     │ │ │ │ │ │ │ └──── joystick a, x coord (0 = timing active)
     │ │ │ │ │ │ └───── joystick a, y coord (0 = timing active)
     │ │ │ │ │ └────── joystick b, x coord (0 = timing active)
     │ │ │ │ └─────── joystick b, y coord (0 = timing active)
     │ │ │ └──────── joystick a, button 1 (0=pressed)
     │ │ └───────── joystick a, button 2 (0=pressed)
     │ └────────── joystick b, button 1 (0=pressed)
     └─────────── joystick b, button 2 (0=pressed)

    │7│6│5│4│3│2│1│0│  Port at 201h used with Paddles
     │ │ │ │ │ │ │ └──── paddle a coord (0 = timing active)
     │ │ │ │ │ │ └───── paddle b coord (0 = timing active)
     │ │ │ │ │ └────── paddle c coord (0 = timing active)
     │ │ │ │ └─────── paddle d coord (0 = timing active)
     │ │ │ └──────── paddle a, button (0=pressed)
     │ │ └───────── paddle b, button (0=pressed)
     │ └────────── paddle c, button (0=pressed)
     └─────────── paddle d, button (0=pressed)


    - accessed through port 201h
    - bits 3-0 are resistive inputs with the length of the pulse
      determined by 0-100K ohm resistive load.   Use this formula:

%    time = 24.2µ + ( 0.011µ * resistance )
    or
%    resistance = ( time - 24.2 ) / 0.011


    - a read should be immediately preceded by a write (any data)
      to start timing for the resistive values.
:Laserjet:HP Laserjet
^Hewlett Packard Laserjet Printer Control Codes

%    Printer Control and Orientation
    ESC E        Reset printer
    ESC z        Self Test
    ESC &l0O    Portrait orientation
    ESC &l1O    Landscape orientation
    ESC (s0P    Select fixed space font
    ESC (s1P    Select proportional font
    ESC (s0S    Set upright character orientation
    ESC (s1S    Set Italic character orientation
    ESC &l#X    Select '#' number of copies
    ESC &l0H    Eject page
    ESC &l1H    Feed paper from tray
    ESC &l2H    Feed paper manually
    ESC &l3H    Feed envelope
    ESC &l0T    Default stacking position
    ESC &l1T    Togglestacking position

%    8 Bit Symbol Set Selection
    ESC (8U     Select Roman 8 symbol set
    ESC (8K     Select Kana 8 symbol set
    ESC (8M     Select Math 8 symbol set

%    7 Bit Symbol Set Selection
    ESC (0U     Select USASCII symbol set
    ESC (0B     Select Line Draw symbol set
    ESC (0A     Select Math symbol set
    ESC (0M     Select Math 7 symbol set
    ESC (0Q     Select Math 8a symbol set
    ESC (1Q     Select Math 8b symbol set
    ESC (1U     Select US Legal symbol set
    ESC (0E     Select Roman Extension symbol set
    ESC (0D     Select ISO Denmark/Norway symbol set
    ESC (1E     Select ISO United Kingdom symbol set
    ESC (0F     Select ISO France symbol set
    ESC (0G     Select ISO German symbol set
    ESC (0I     Select ISO Italy symbol set
    ESC (0S     Select ISO Sweden/Finland symbol set
    ESC (1S     Select ISO Spain symbol set
    ESC (15U    Select PiFont symbol set
    ESC (2Q     Select PiFonta symbol set

%    Font Management
    ESC (s3T     Select Courier font
    ESC (s0T     Select Line Printer font
    ESC (s1T     Select Pica font
    ESC (s2T     Select Elite font
    ESC (s4T     Select Helvetica font
    ESC (s5T     Select Times Roman (TMS RMN) font
    ESC (s6T     Select Gothic font
    ESC (s7T     Select Script font
    ESC (s8T     Select Prestige font
    ESC *c#D     Specify font ID '#'
    ESC *c#E     Specify character code '#'
    ESC *c0F     Delete all fonts, including permanent
    ESC *c1F     Delete all temporary fonts
    ESC *c2F     Delete last font ID specified
    ESC *c3F     Delete last character code and font ID specified
    ESC *c4F     Make last font ID temporary
    ESC *c5F     Make last font ID permanent
    ESC *c6F     Copy or assign last font ID specified
    ESC *c7F     Reestablish ROM
    ESC *c8F     Set primary font
    ESC *c9F     Set secondary font
    ESC *c10F     Set primary and secondary font default
    ESC )s#W <data>  Create font header
    ESC (s#W <data>  Download character
    ESC (#X <data>     Designate downloaded font as primary
    ESC )#X <data>     Designate downloaded font as secondary
    ESC (#@      Primary font default (see printer manual)
    ESC )#@      Secondary font default(see printer manual)

%    Pitch and Point Selection
    ESC (s10H    Set 10 pitch
    ESC (s12H    Set 12 pitch
    ESC (s16.6H    Set 16.66 pitch

    ESC (s7V    Set point size to 7
    ESC (s8V    Set point size to 8
    ESC (s8.5V    Set point size to 8.5
    ESC (s10V    Set point size to 10
    ESC (s12V    Set point size to 12
    ESC (s14.4V    Set point size to 14.4

%    Page Dimensions
    ESC &l#P    Set page length to '#' lines
    ESC &l#E    Set top margin to '#' lines
    ESC &l#F    Set text length to '#' lines
    ESC 9        Clear margins
    ESC &a#L    Set left margin to column '#'
    ESC &a#M    Set right margin to column '#'
    ESC &l#C    Set vertical motion index to '#' 1/48" increments
    ESC &l#D    Set lines per inch to '#', valid values are:
            1, 2, 3, 4, 6, 8, 12, 16 or 24
    ESC &k#H    Set horizontal motion index where # is derived
            using    # = (120.0 / cpi)     (1/10 precision)

%    Cursor Positioning
    ESC &a#R    Move to row '#'
    ESC &a#C    Move to col '#'
    ESC &a#H    Move to horizontal position '#' in decipoints
    ESC &a#V    Move to vertical position '#' in decipoints
    ESC *p#X    Move to horizontal position '#' in dots
    ESC *p#Y    Move to vertical position '#' in dots
    ESC &f0S    Push cursor position
    ESC &f1     Pop cursor position

%    Raster Graphics
    ESC *t75R      Select 75 dots per inch graphics mode
    ESC *t100R      Select 100 dots per inch graphics mode
    ESC *t150R      Select 150 dots per inch graphics mode
    ESC *t300R      Select 300 dots per inch graphics mode
    ESC *r0A      Start graphics at left most position
    ESC *r1A      Start graphics at current cursor
    ESC *b#W <data>   Transfer '#' byte raster image as stream "<data>"
    ESC *rB       End graphics

%    Advanced Graphics
    ESC *c#A      Set horizontal rule/pattern size in dots
    ESC *c#H      Set horizontal rule/pattern size in decipoints
    ESC *c#B      Set vertical rule/pattern size in dots
    ESC *c#V      Set vertical rule/pattern size in decipoints
    ESC *c0P      Select black rule
    ESC *c2P      Select gray scale pattern
    ESC *c3P      Select HP-Defined pattern
    ESC *c#G      Set grey scale pattern, where # is a value between
              [0..6] for HP defined patterns and [0..100] to
              specify percentage gray scaling.  The mode depends
              on the rule/pattern selected using ESC *c?P
    ESC *c1G      Vertical lines pattern
    ESC *c2G      Horizontal lines pattern
    ESC *c3G      Diagonal lines pattern (upward left to right)
    ESC *c4G      Diagonal lines pattern (downward left to right)
    ESC *c5G      Horizontal/vertical grid lines pattern
    ESC *c6G      Diagonal grid pattern
    ESC *c#G      Set gray scaling to '#' percent

%    Macro commands
    ESC &f#Y      Identify macro as ID "#'
    ESC &f0X      Start macro definition
    ESC &f1X      Stop macro definition
    ESC &f2X      Execute macro
    ESC &f3X      Call macro
    ESC &f4X      Enable auto macro overlay
    ESC &f5X      Disable auto macro overlay
    ESC &f6X      Delete all macros
    ESC &f7X      Delete all temporary macros
    ESC &f8X      Delete macro ID
    ESC &f9X      Make macro temporary
    ESC &f10X      Make macro permanent

%    Miscellaneous
    ESC (s#B      Set stroke weight '#'=(7..-7), 7=bold, -7=light
    ESC &dD       Set underline on
    ESC &d@       Set underline off
    ESC =          Half line feed
    ESC Y          Turn display functions mode on
    ESC Z          Turn display functions mode off (default)
    ESC &p#X <data>   Disable command interpretation for the '#' bytes
              following this command
    ESC &l0L      Disable perforation skip
    ESC &l1L      Enable perforation skip
    ESC &k0G      Set line terminators to CR=CR, LF=LF, FF=FF
    ESC &k1G      Set line terminators to CR=CR+LF, LF=LF, FF=FF
    ESC &k2G      Set line terminators to CR=CR, LF=CR+LF, FF=CR+FF
    ESC &k3G      Set line terminators to CR=CR+LF, LF=CR+LF, FF=CR+FF
    ESC &s0C      Enable end of line wrap
    ESC &s1C      Disable end of line wrap


%    Escape sequence combination rules:

     1. The first 2 characters following the ESC must be the same.
     2. The final character in any sequence other than the last must be
        changed to lower case.
     3. The last character in the complete sequence must be changed to
        upper case.
     4. Escape sequences must be specified in the order in which they
        should be performed.


    - the space following ESC is not included in the string
:keyboard commands
^Keyboard Commands & Responses

^Commands System Issues to Keyboard (via 8042 port 60h)

    ED  Set/Reset Mode Indicators, keyboard responds with ACK then
        waits for a following option byte.    When the option byte is
        received the keyboard again ACK's and then sets the LED's
        accordingly.  Scanning is resumed if scanning was enabled.
        If another command is received instead of the option byte
        (high bit set on) this command is terminated.  Hardware
        defaults to these indicators turned off.

        │7-3│2│1│0│ Keyboard Status Indicator Option Byte
          │  │ │ └─── Scroll-Lock indicator  (0=off, 1=on)
          │  │ └──── Num-Lock indicator  (0=off, 1=on)
          │  └───── Caps-Lock indicator  (0=off, 1=on)
          └─────── reserved (must be zero)

    EE  Diagnostic Echo, keyboard echoes the EE byte back to the system
        without an acknowledgement.
    F0  PS/2 Select/Read Alternate Scan Code Sets, instructs keyboard
        to use one of the three make/break scan code sets.     Keyboard
        responds by clearing the output buffer/typematic key and then
        transmits an ACK.  The system must follow up by sending an
        option byte which will again be ACK'ed by the keyboard:

          00  return byte indicating scan code set in use
          01  select scan code set 1  (used on PC & XT)
          02  select scan code set 2
          03  select scan code set 3

    F2  PS/2 Read Keyboard ID, keyboard responds with an ACK and a two
        byte keyboard ID of 83AB.
    F3  Set Typematic Rate/Delay, keyboard responds with ACK and waits
        for rate/delay byte.   Upon receipt of the rate/delay byte the
        keyboard responds with an ACK, then sets the new typematic
        values and scanning continues if scanning was enabled.

        │7│6│5│4│3│2│1│0│  Typematic Rate/Delay Option Byte
         │ │ │ ├─┼─┼─┼─┼──── typematic rate indicator (see ~INT 16,3~)
         │ │ │ │ │ └─┴─┴─── A in period formula (see below)
         │ │ │ └─┴──────── B is period formula (see below)
         │ └─┴─────────── typematic delay
         └────────────── always zero

        delay = (rate+1) * 250   (in milliseconds)
        rate = (8+A) * (2**B) * 4.17  (in seconds, ± 20%)

        Defaults to 10.9 characters per second and a 500ms delay.  If a
        command byte (byte with high bit set) is received instead of an
        option byte this command is cancelled.
    F4  Enable Keyboard, cause the keyboard to clear its output buffer
        and last typematic key and then respond with an ACK.  The
        keyboard then begins scanning.
    F5  Default w/Disable, resets keyboard to power-on condition by
        clearing the output buffer, resetting typematic rate/delay,
        resetting last typematic key and setting default key types.
        The keyboard responds with an ACK and waits for the next
        instruction.
    F6  Set Default, resets to power-on condition by clearing the output
        buffer, resetting typematic rate/delay and last typematic key
        and sets default key types.  The keyboard responds with an ACK
        and continues scanning.
    F7  PS/2 Set All Keys to Typematic, keyboard responds by sending an
        ACK, clearing its output buffer and setting the key type to
        Typematic.     Scanning continues if scanning was enabled.  This
        command may be sent while using any Scan Code Set but only has
        effect when Scan Code Set 3 is in use.
    F8  PS/2 Set All Keys to Make/Break, keyboard responds by sending an
        ACK, clearing its output buffer and setting the key type to
        Make/Break.  Scanning continues if scanning was enabled.  This
        command may be sent while using any Scan Code Set but only has
        effect when Scan Code Set 3 is in use.
    F9  PS/2 Set All Keys to Make, keyboard responds by sending an ACK,
        clearing its output buffer and setting the key type to Make.
        Scanning continues if scanning was enabled.  This command may
        be sent while using any Scan Code Set but only has effect when
        Scan Code Set 3 is in use.
    FA  PS/2 Set All Keys to Typematic Make/Break, keyboard responds by
        sending an ACK, clearing its output buffer and setting the key
        type to Typematic Make/Break.  Scanning continues if scanning
        was enabled.  This command may be sent while using any Scan Code
        Set but only has effect when Scan Code Set 3 is in use.
    FB  PS/2 Set Key Type to Typematic, keyboard responds by sending an
        ACK, clearing its output buffer and then waiting for the key ID
        (make code from Scan Code Set 3).  The specified key type is then
        set to typematic.    This command may be sent while using any
        Scan Code Set but only has effect when Scan Code Set 3 is in use.
    FC  PS/2 Set Key Type to Make/Break, keyboard responds by sending an
        ACK, clearing its output buffer and then waiting for the key ID
        (make code from Scan Code Set 3).  The specified key type is then
        set to Make/Break.     This command may be sent while using any Scan
        Code Set but only has effect when Scan Code Set 3 is in use.
    FD  PS/2 Set Key Type to Make, keyboard responds by sending an ACK,
        clearing its output buffer and then waiting for the key ID (make
        code from Scan Code Set 3).  The specified key type is then set
        to Make.  This command may be sent while using any Scan Code Set
        but only has effect when Scan Code Set 3 is in use.
    FE  Resend, should be sent when a transmission error is detected
        from the keyboard
    FF  Reset, Keyboard sends ACK and waits for system to receive it
        then begins a program reset and Basic Assurance Test (BAT).
        Keyboard returns a one byte completion code then sets default
        Scan Code Set 2.


^Keyboard Responses to System (via 8042 port 60h)

    00  Key Detection Error or Overrun Error for Scan Code Set 1,
        replaces last key in the keyboard buffer if the buffer is full.
    AA  BAT Completion Code, keyboard sends this to indicate the keyboard
        test was successful.
    EE  Echo Response, response to the Echo command.
    F0  Break Code Prefix in Scan Code Sets 2 and 3.
    FA  Acknowledge, keyboard sends this whenever a valid command or
        data byte is received (except on Echo and Resend commands).
    FC  BAT Failure Code, keyboard sends this to indicate the keyboard
        test failed and stops scanning until a response or reset is sent.
    FE  Resend, keyboard request resend of data when data sent to it is
        invalid or arrives with invalid parity.
    FF  Key Detection Error or Overrun Error for Scan Code Set 2 or 3,
        replaces last key in the keyboard buffer if the buffer is full.
    id  Keyboard ID Response, keyboard sends a two byte ID after ACK'ing
        the Read ID command.  The byte stream contains 83AB in LSB, MSB
        order.  The keyboard then resumes scanning.


    - command F7 through FD are NOP's on the AT and are ACK'ed but not
      acted upon
    - see    ~8042~  ~MAKE CODES~  ~BREAK CODES~  ~INT 16,3~
:parallel port:printer port
^Parallel Printer Port

%    Port 3BC printer data output  (readable)

     │7│6│5│4│3│2│1│0│  ports 278, 378, 3BC
      │ │ │ │ │ │ │ └──── data bit 0, hardware pin 2
      │ │ │ │ │ │ └───── data bit 1, hardware pin 3
      │ │ │ │ │ └────── data bit 2, hardware pin 4
      │ │ │ │ └─────── data bit 3, hardware pin 5
      │ │ │ └──────── data bit 4, hardware pin 6
      │ │ └───────── data bit 5, hardware pin 7
      │ └────────── data bit 6, hardware pin 8
      └─────────── data bit 7, hardware pin 9

%    Port 3BD printer status register   (Parallel Printer Port)

     │7│6│5│4│3│2│1│0│  ports 279, 379, 3BD
      │ │ │ │ │ │ │ └──── 1 = time-out
      │ │ │ │ │ └─┴───── unused
      │ │ │ │ └──────── 1 = error,    pin 15
      │ │ │ └───────── 1 = on-line,  pin 13
      │ │ └────────── 1 = out of paper,  pin 12
      │ └─────────── 0 = Acknowledge,  pin 10
      └──────────── 0 = busy,  pin 11

%    Port 3BE printer control register   (Parallel Printer Port)

     │7│6│5│4│3│2│1│0│  ports 27A, 37A, 3BE
      │ │ │ │ │ │ │ └──── 1 = output data to printer,  (pin 1)
      │ │ │ │ │ │ └───── 1 = auto line feed,  (pin 14)
      │ │ │ │ │ └────── 0 = initialize printer,  (pin 16)
      │ │ │ │ └─────── 1 = printer reads output,  (pin 17)
      │ │ │ └──────── 0 = IRQ disable,1=IRQ enable for ACK
      └─┴─┴───────── unused

:ports:port addresses:hardware ports
^PORTS    Common I/O Port Addresses

    Port addresses are not always constant across PC, AT and PS/2
    Unless marked, port addresses are relative to PC and XT only

%    000-00F  8237 DMA controller
    000 Channel 0 address register
    001 Channel 0 word count
    002 Channel 1 address register
    003 Channel 1 word count
    004 Channel 2 address register
    005 Channel 2 word count
    006 Channel 3 address register
    007 Channel 3 word count
    008 Status/command register
    009 Request register
    00A Mask register
    00B Mode register
    00C Clear MSB/LSB flip flop
    00D Master clear temp register
    00E Clear mask register
    00F Multiple mask register

%    010-01F  8237 DMA Controller (PS/2 model 60 & 80), reserved (AT)

%    020-02F  8259A Master Programmable Interrupt Controller
    020 8259 Command port  (see ~8259~)
    021 8259 Interrupt mask register  (see 8259)

%    030-03F  8259A Slave Programmable Interrupt Controller (AT,PS/2)

%    040-05F  8253 or 8254 Programmable Interval Timer (PIT, see ~8253~)
    040 8253 channel 0, counter divisor
    041 8253 channel 1, RAM refresh counter
    042 8253 channel 2, Cassette and speaker functions
    043 8253 mode control  (see ~8253~)
    044 8254 PS/2 extended timer
    047 8254 Channel 3 control byte

%    060-067  8255 Programmable Peripheral Interface  (PC,XT, PCjr)
    060 8255 Port A keyboard input/output buffer (output PCjr)
    061 8255 Port B output
    062 8255 Port C input
    063 8255 Command/Mode control register

%    060-06F  8042 Keyboard Controller  (AT,PS/2)
    060 8042 Keyboard input/output buffer register
    061 8042 system control port (for compatability with 8255)
    064 8042 Keyboard command/status register

    070 CMOS RAM/RTC, also NMI enable/disable (AT,PS/2, see ~RTC~)
    071 CMOS RAM data  (AT,PS/2)

    080 Manufacturer systems checkpoint port (used during POST)
%    080-090  DMA Page Registers
    081 High order 4 bits of DMA channel 2 address
    082 High order 4 bits of DMA channel 3 address
    083 High order 4 bits of DMA channel 1 address

%    090-097  POS/Programmable Option Select  (PS/2)
    090 Central arbitration control Port
    091 Card selection feedback
    092 System control and status register
    094 System board enable/setup register
    095 Reserved
    096 Adapter enable/setup register
    097 Reserved

    0A0 NMI Mask Register (PC,XT) (write 80h to enable NMI, 00h disable)
%    0A0-0BF  Second 8259 Programmable Interrupt Controller (AT, PS/2)
    0A0 Second 8259 Command port  (see ~8259~)
    0A1 Second 8259 Interrupt mask register  (see 8259)

    0C0 TI SN76496 Programmable Tone/Noise Generator (PCjr)
%    0C0-0DF  8237 DMA controller 2 (AT)
    0C2 DMA channel 3 selector  (see ports 6 & 82)

    0E0-0EF  Reserved

%    0F0-0FF  Math coprocessor (AT, PS/2)
%    0F0-0F5  PCjr Disk Controller
    0F0 Disk Controller
    0F2 Disk Controller control port
    0F4 Disk Controller status register
    0F5 Disk Controller data port

%    0F8-0FF  Reserved for future microprocessor extensions

%    100-10F  POS Programmable Option Select (PS/2)
    100 POS Register 0, Adapter ID byte (LSB)
    101 POS Register 1, Adapter ID byte (MSB)
    102 POS Register 2, Option select data byte 1
        Bit 0 is card enable (CDEN)
    103 POS Register 3, Option select data byte 2
    104 POS Register 4, Option select data byte 3
    105 POS Register 5, Option select data byte 4
        Bit 7 is (-CHCK)
        Bit 6 is reserved
    106 POS Register 6, subaddress extension (LSB)
    107 POS Register 7, subaddress extension (MSB)

%    110-1EF  System I/O channel

%    170-17F  Fixed disk 1 (AT)
    170 disk 1 data
    171 disk 1 error
    172 disk 1 sector count
    173 disk 1 sector number
    174 disk 1 cylinder low
    175 disk 1 cylinder high
    176 disk 1 drive/head
    177 disk 1 status

%    1F0-1FF  Fixed disk 0 (AT)
    1F0 disk 0 data
    1F1 disk 0 error
    1F2 disk 0 sector count
    1F3 disk 0 sector number
    1F4 disk 0 cylinder low
    1F5 disk 0 cylinder high
    1F6 disk 0 drive/head
    1F7 disk 0 status

%    200-20F  Game Adapter (see GAME PORT or ~JOYSTICK~)

%    210-217  Expansion Card Ports (XT)
    210 Write: latch expansion bus data
        read:  verify expansion bus data
    211 Write: clear wait,test latch
        Read:  MSB of data address
    212 Read:  LSB of data address
    213 Write: 0=enable, 1=/disable expansion unit
    214-215  Receiver Card Ports
    214 write: latch data, read: data
    215 read:  MSB of address, next read: LSB of address

    21F Reserved

%    220-26F  Reserved for I/O channel

%    270-27F  Third parallel port (see ~PARALLEL PORT~)
    278 data port
    279 status port
    27A control port

%    280-2AF  Reserved for I/O channel

%    2A2-2A3  MSM58321RS clock

%    2B0-2DF  Alternate EGA, or 3270 PC video (XT, AT)

    2E0 Alternate EGA/VGA
    2E1 GPIB Adapter  (AT)

%    2E2-2E3  Data acquisition adapter (AT)

%    2E8-2EF  COM4 non PS/2 UART (Reserved by IBM) (see ~UART~)

%    2F0-2F7  Reserved

%    2F8-2FF  COM2 Second Asynchronous Adapter (see UART)
         Primary Asynchronous Adapter for PCjr

%    300-31F  Prototype Experimentation Card (except PCjr)
         Periscope hardware debugger
%    320-32F  Hard Disk Controller  (XT)
    320 Read from/Write to controller
    321 Read: Controller Status, Write: controller reset
    322 Write: generate controller select pulse
    323 Write: Pattern to DMA and interrupt mask register
        (see ports 0F,21,C2)
    324 disk attention/status

%    330-33F  Reserved for XT/370

%    340-35F  Reserved for I/O channel

%    360-36F  PC Network

%    370-377  Floppy disk controller (except PCjr)
    372 Diskette digital output
    374 Diskette controller status
    375 Diskette controller data
    376 Diskette controller data
    377 Diskette digital input

%    378-37F  Second Parallel Printer (see ~PARALLEL PORT~)
         First Parallel Printer (see PARALLEL PORT)
    378 data port
    379 status port
    37A control port

%    380-38F  Secondary Binary Synchronous Data Link Control (SDLC) adapter
    380 On board 8255 port A, internal/external sense
    381 On board 8255 port B, external modem interface
    382 On board 8255 port C, internal control and gating
    383 On board 8255 mode register
    384 On board 8253 channel square wave generator
    385 On board 8253 channel 1 inactivity time-out
    386 On board 8253 channel 2 inactivity time-out
    387 On board 8253 mode register
    388 On board 8273 read: status; Write: Command
    389 On board 8273 write: parameter; read: response
    38A On board 8273 transmit interrupt status
    38B On board 8273 receiver interrupt status
    38C On board 8273 data

%    390-39F  Cluster Adapter

%    3A0-3AF  Primary Binary Synchronous Data Link Control (SDLC) adapter
    3A0 On board 8255 port A, internal/external sense
    3A1 On board 8255 port B, external modem interface
    3A2 On board 8255 port C, internal control and gating
    3A3 On board 8255 mode register
    3A4 On board 8253 counter 0 unused
    3A5 On board 8253 counter 1 inactivity time-outs
    3A6 On board 8253 counter 2 inactivity time-outs
    3A7 On board 8253 mode register
    3A8 On board 8251 data
    3A9 On board 8251 command/mode/status register

%    3B0-3BF Monochrome Display Adapter (write only, see ~6845~)
    3B0 port address decodes to 3B4
    3B1 port address decodes to 3B5
    3B2 port address decodes to 3B4
    3B3 port address decodes to 3B5
    3B4 6845 index register, selects which register [0-11h]
        is to be accessed through port 3B5
    3B5 6845 data register [0-11h] selected by port 3B4,
        registers 0C-0F may be read.  If a read occurs without
        the adapter installed, FFh is returned.  (see 6845)
    3B6 port address decodes to 3B4
    3B7 port address decodes to 3B5
    3B8 6845 Mode control register
    3B9 reserved for color select register on color adapter
    3BA status register (read only)
    3BB reserved for light pen strobe reset

%    3BC-3BF  Primary Parallel Printer Adapter (see ~PARALLEL PORT~)
    3BC parallel 1, data port
    3BD parallel 1, status port
    3BE parallel 1, control port

%    3C0-3CF  EGA/VGA
    3C0 VGA attribute and sequencer register
    3C1 Other video attributes
    3C2 EGA, VGA, CGA input status 0
    3C3 Video subsystem enable
    3C4 CGA, EGA, VGA sequencer index
    3C5 CGA, EGA, VGA sequencer
    3C6 VGA video DAC PEL mask
    3C7 VGA video DAC state
    3C8 VGA video DAC PEL address
    3C9 VGA video DAC
    3CA VGA graphics 2 position
    3CC VGA graphics 1 position
    3CD VGA feature control
    3CE VGA graphics index
    3CF Other VGA graphics

%    3D0-3DF Color Graphics Monitor Adapter (ports 3D0-3DB are
        write only, see 6845)
    3D0 port address decodes to 3D4
    3D1 port address decodes to 3D5
    3D2 port address decodes to 3D4
    3D3 port address decodes to 3D5
    3D4 6845 index register, selects which register [0-11h]
        is to be accessed through port 3D5
    3D5 6845 data register [0-11h] selected by port 3D4,
        registers 0C-0F may be read.  If a read occurs without
        the adapter installed, FFh is returned.  (see ~6845~)
    3D6 port address decodes to 3D4
    3D7 port address decodes to 3D5
    3D8 6845 Mode control register (CGA, EGA, VGA, except PCjr)
    3D9 color select palette register (CGA, EGA, VGA, see 6845)
    3DA status register (read only, see 6845, PCjr VGA access)
    3DB Clear light pen latch (any write)
    3DC Preset Light pen latch
    3DF CRT/CPU page register (PCjr only)

%    3E8-3EF  COM3 non PS/2 UART (Reserved by IBM) (see ~UART~)

%    3F0-3F7  Floppy disk controller (except PCjr)
    3F0 Diskette controller status A
    3F1 Diskette controller status B
    3F2 controller control port
    3F4 controller status register
    3F5 data register (write 1-9 byte command, see ~INT 13~)
    3F6 Diskette controller data
    3F7 Diskette digital input

%    3F8-3FF  COM1 Primary Asynchronous Adapter  (see ~UART~)

    3220-3227  PS/2 COM3 (see UART)
    3228-322F  PS/2 COM4 (see UART)
    4220-4227  PS/2 COM5 (see UART)
    4228-422F  PS/2 COM6 (see UART)
    5220-5227  PS/2 COM7 (see UART)
    5228-522F  PS/2 COM8 (see UART)

    - many cards designed for the ISA ~BUS~ only uses the lower 10 bits
      of the port address but some ISA adapters use addresses beyond
      3FF.  Any address that matches in the lower 10 bits will decode
      to the same card.   It is up to the adapters to resolve or ignore
      the high bits of the port addresses.   An example would be the
      Cluster adapter that has a port address of 390h.  The second
      cluster adapter has a port address of 790h which resolves to
      the same port address with the cards determining which one
      actually gets the data.
:diagnostic codes:POST errors
^DIAGS    IBM PC Diagnostic Error Codes

%    Code       Description      (Diagnostic Error Codes)

     1x   undetermined problem errors
     2x   power supply errors
     61   battery error (PS/2)
     62   configuration changed but no adaptors changed or CRC error
     63   memory size during POST does not match ~CMOS~ RAM
     65   card Id's in CMOS do not match system

%    1xx   System Board Errors
    101   system board failed
    102   BIOS ROM checksum error (PC, XT), Timer (AT)
    103   BASIC ROM checksum error (PC, XT), Timer interrupt (AT)
    104   interrupt controller (PC, XT), Protected mode (AT)
    105   timer (PC,XT), Last ~8042~ command not accepted (AT)
    106   converting logic test failure
    107   adapter card or math coprocessor (NMI)
    108   timer bus test
    109   DMA test error
    110   system board memory error (PS/2)
    111   adapter memory
    112   system unit adapter failure
    114   system unit and adapter card unit failure (PS/1)
    121   unexpected hardware interrupt
    131   cassette wrap test failed
    151   real-time clock, CMOS RAM or battery
    152   real-time clock
    161   system options error, battery failure
    162   CMOS RAM configuration error
    163   CMOS time and date not set
    164   system memory configuration is incorrect
    165   adapter added/removed
    199   user indicated configuration not correct

%    2xx   RAM Errors
    201   memory test error
    202   memory address error (Line error    0 - 15)
    203   memory address error (Line error 16 - 23)
    216   motherboard memory

%    3xx   Keyboard Errors
    301   keyboard did not respond to software reset or a stuck
          (number preceding 301 is scan code for stuck key)
    302   user indicated keyboard error or AT system unit is locked
    303   keyboard or system board error
    304   keyboard or system board error; CMOS does not match system
    341   replace keyboard
    342   replace keyboard interface cable
    343   replace enhancement card or cable
    365   keyboard (replace keyboard)
    366   interface cable (replace cable)
    367   enhancement card or cable (replace)

%    4xx   Monochrome Monitor Errors
    401   monochrome memory test, horizontal sync frequency
          test, or video test failed
    408   user indicated display attributes failure
    416   user indicated character set failure
    424   user indicated 80x25 mode failure
    432   parallel port test failed (monochrome adapter)

%    5xx   Color Monitor Errors
    501   CGA memory test failed, horizontal sync frequency test, or
          video test failed
    508   user indicated display attribute failure
    516   user indicated character set failure
    524   user indicated 80x25 mode failure
    532   user indicated 40x25 mode failure
    540   user indicated 320x200 graphics mode failure
    548   user indicated 640x200 graphics mode failure
    556   light pen test
    564   user indicated screen paging test

%    6xx   Diskette Drive/Adapter Errors
    601   diskette power on diagnostics test failed
    602   diskette test failed (boot record not valid)
    603   diskette size error
    606   diskette verify function failed
    607   write protected diskette
    608   bad command diskette status returned
    610   diskette initialization failed
    611   time-out - diskette status returned
    612   bad NEC ~FDC~ - diskette status returned
    613   bad DMA - diskette status returned
    614   DMA boundary error
    621   bad seek - diskette status returned
    622   bad CRC - diskette status returned
    623   record not found - diskette status returned
    624   bad address mark - diskette status returned
    625   bad NEC seek - diskette status returned
    626   diskette data compare error
    627   diskette change line error
    628   diskette removed

%    7xx   8087 Math Coprocessor
    701   coprocessor test failure

%    9xx   Parallel Printer Adapter Errors
    901   parallel printer adapter test failed

%    10xx  Alternate Parallel Printer Adapter
    1001  alternate printer adapter test failure

%    11xx  Asynchronous Communications Adapter Errors
    1101  asynchronous communications adapter test failed
    1110  modem status register not clear
    1111  ring-indicate
    1112  trailing edge ring-indicate
    1113  receive and delta receive line signal detect
    1114  receive line signal detect
    1115  delta receive line signal detect
    1116  line control register: all bits cannot be set
    1117  line control register: all bits cannot be reset
    1118  transmit holding and/or shift register stuck on
    1119  data ready stuck on
    1120  interrupt enable register: all bits cannot be set
    1121  interrupt enable register: all bits cannot be reset
    1122  interrupt pending stuck on
    1123  interrupt ID register stuck on
    1124  modem control register: all bits cannot be set
    1125  modem control register: all bits cannot be reset
    1126  modem status register: all bits cannot be set
    1127  modem status register: all bits cannot be reset
    1128  interrupt ID
    1129  cannot force overrun error
    1130  no modem status interrupt
    1131  invalid interrupt pending
    1132  no data ready
    1133  no data available interrupt
    1134  no transmit holding interrupt
    1135  no interrupts
    1136  no received line status interrupt
    1137  no receive data available
    1138  transmit holding register not empty
    1139  no modem status interrupt
    1140  transmit holding register not empty
    1141  no interrupts
    1142  no IRQ4 interrupt
    1143  no IRQ3 interrupt
    1144  no data transferred
    1145  maximum baud rate
    1146  minimum baud rate
    1148  time-out error
    1149  invalid data returned
    1150  modem status register error
    1151  no DSR and delta DSR
    1152  no DSR
    1153  no delta DSR
    1154  modem status register not clear
    1155  no CTS and delta CTS
    1156  no CTS
    1157  no delta CTS

%    12xx  Alternate Asynchronous Communications Adapter
    1200-1257 same as 1100-1157

%    13xx  Game Control Adapter Errors
    1301  game control adapter test failed
    1302  joystick test failed
    1380  audio card and joystick (PS/1)

%    14xx  Printer Errors
    1401  printer test failed
    1404  matrix printer failed

%    15xx  SDLC Communications Adapter Errors
    1501  adapter test failure
    1510  8255 port b failure
    1511  8255 port a failure
    1512  8255 port c failure
    1513  8253 timer 1 did not reach terminal count
    1514  8253 timer 1 stuck on
    1515  8253 timer 0 did not reach terminal count
    1516  8253 timer 0 stuck on
    1517  8253 timer 2 did not reach terminal count
    1518  8253 timer 2 stuck on
    1519  8273 port b error
    1520  8273 port a error
    1521  8273 command/read time-out
    1522  interrupt level 4 failure
    1523  ring Indicate stuck on
    1524  receive clock stuck on
    1525  transmit clock stuck on
    1526  test indicate stuck on
    1527  ring indicate not on
    1528  receive clock not on
    1529  transmit clock not on
    1530  test indicate not on
    1531  DSR not on
    1532  CD not on
    1533  CTS not on
    1534  DSR stuck on
    1535  CD stuck on
    1536  CTS stuck on
    1537  level 3 interrupt failure
    1538  receive interrupt results error
    1539  wrap data compare error
    1540  DMA channel 1 error
    1541  DMA channel 1 error
    1542  error in 8273 error checking or status reporting
    1547  stray interrupt level 4
    1548  stray interrupt level 3
    1549  interrupt presentation sequence time-out

%    16xx  Display Emulation Errors (327x, 5520, 525x)

%    17xx  Fixed Disk Errors
    1701  post error
    1702  adapter error
    1703  drive error (seek)
    1704  adapter or drive error
    1705  no record found
    1706  write fault error
    1707  track 0 error
    1708  head select error
    1709  defective error check
    1710  read buffer overrun
    1711  bad address mark
    1712  undetermined error
    1713  data compare error
    1714  drive not ready
    1780  disk 0 failure
    1781  disk 1 failure
    1782  disk controller failure
    1790  fixed disk 0 error
    1791  fixed disk 1 error

%    18xx  I/O Expansion Unit Errors
    1801  I/O expansion unit POST error
    1810  enable/disable failure
    1811  extender card wrap test failed (disabled)
    1812  high order address lines failure (disabled)
    1813  wait state failure (disabled)
    1814  enable/disable could not be set on
    1815  wait state failure (enabled)
    1816  extender card wrap test failed (enabled)
    1817  high order address lines failure (enabled)
    1818  disable not functioning
    1819  wait request switch not set correctly
    1820  receiver card wrap test failure
    1821  receiver high order address lines failure

%    19xx  3270 PC Attachment Card Errors

%    20xx  Bisync Communications Adapter Errors
    2010  8255 port a failure
    2011  8255 port b failure
    2012  8255 port c failure
    2013  8253 timer 1 did not reach terminal count
    2014  8253 timer 1 stuck on
    2016  8253 timer 2 didn't reach terminal count or timer 2 stuck on
    2017  8251 DSR failed to come on
    2018  8251 CTS not sensed
    2019  8251 DSR stuck on
    2020  8251 CTS stuck on
    2021  8251 hardware reset failed
    2022  8251 software reset failed
    2023  8251 software error reset failed
    2024  8251 transmit ready did not come on
    2025  8251 receive ready did not come on
    2026  8251 could not force "overrun" error status
    2027  interrupt failure, no timer interrupt
    2028  transmit interrupt, card or planar failure
    2029  transmit interrupt, card failure
    2030  receive interrupt, card or planar failure
    2031  receive interrupt, card failure
    2033  ring indicate stuck on
    2034  receive clock stuck on
    2035  transmit clock stuck on
    2036  test indicate stuck on
    2037  ring indicate stuck on
    2038  receive clock not on
    2039  transmit clock not on
    2040  test indicate not on
    2041  DSR not on
    2042  CD not on
    2043  CTS not on
    2044  DSR stuck on
    2045  CD stuck on
    2046  CTS stuck on
    2047  unexpected transmit interrupt
    2048  unexpected receive interrupt
    2049  transmit data did not equal receive data
    2050  8251 detected overrun error
    2051  lost DSR during data wrap
    2052  receive time-out during data wrap

%    21xx  Alternate Bisync Communications Adapter Errors
    2100-2152 same as 2000-2052

%    22xx  Cluster Adapter Errors

%    24xx  EGA Errors
    2401  adapter test failure
    2408  user-indicated display attributes
    2416  user-indicated character set
    2424  user-indicated 80x25 mode
    2432  user-indicated 40x25 mode
    2440  user-indicated 320x200 graphics mode
    2448  user-indicated 640x200 graphics mode
    2456  light pen test
    2464  user-indicated screen paging test

%    2501  EGA Display Error

%    28xx  3278/79 Emulator Adapter (PC, XT)

%    29xx  Color Matrix Printer Errors

%    30xx  Local Area Network Adapter

%    31xx  Alternate Local Area Network Adapter

%    33xx  Compact Printer Errors

%    36xx  IEEE 488 Adapter

%    37xx  Reserved for Future Use

%    38xx  Data Acquisition Adapter

%    39xx  PGA Display and/or Adapter

%    48xx  Internal Modem

%    49xx  Alternate Internal Modem

%    71xx  Voice Communications Adapter

%    73xx  3.5 Inch Diskette Drive
    7301  diskette drive/adapter test failure
    7306  diskette change line error
    7307  write-protected diskette
    7308  bad command
    7310  track zero error
    7311  timeout
    7312  bad NEC7313 bad DMA
    7314  DMA boundary error
    7315  bad index
    7316  speed error
    7321  bad seek
    7322  bad CRC
    7323  record not found
    7324  bad address mark
    7325  bad NEC seek

%    86xx  PS/1 Mouse Error


    - all error codes for the diagnostic and advanced diagnostic
      packages for the PC, XT and AT are represented with the device
      number followed by two digits other than 00.    The device number
      plus 00 represents successful completion of the test.

:resistor values
^Resistor Color Code Chart

%         Color     Digit     Multiplier

         Black     0      1
         Brown     1      10
         Red     2      100         Gold      ± 5% tolerance
         Orange     3      1,000      Silver   ±10% tolerance
         Yellow     4      10,000
         Green     5      100,000
         Blue     6      1,000,000
         Violet     7      10,000,000
         Gray     8      100,000,000
         White     9      1,000,000,000

%          ╒═████░██▒██▓██░████═╕
%          ┴            ┴
            │  │  │  │
            │  │  │  └────────── tolerance (gold or silver)
            │  │  └──────────── Ohm value multiplier
            └──┴────────────── first 2 digits of Ohm value
:RS232 pins:serial ports
^RS232    Communication Configuration

%        IBM PC                IBM AT
%    Pin  25-Pin Signal (DTE)     Pin  9-Pin Signal (DTE)

      1   Chassis Ground  (GND)     1   Carrier Detect (CD)
      2   Transmit Data (TD)     2   Receive Data (RD)
      3   Receive Data (RD)      3   Transmit Data (TD)
      4   Request to Send (RTS)     4   Data Terminal Ready (DTR)
      5   Clear to Send (CTS)     5   Signal Ground (SG)
      6   Data Set Ready (DSR)     6   Data Set Ready (DSR)
      7   Signal Ground (SG)     7   Request to Send (RTS)
      8   Carrier Detect (CD)     8   Clear to Send (CTS)
    9-19  (not used)         9   Ring Indicator (RI)
     20   Data Terminal Ready (DTR)
     22   Ring Indicator (RI)

    There are two general cable configurations used with the RS-232C
    Communications Standard:

      Data Terminal Equipment (DTE): IBM PC's, printers, plotters, etc
      Data Communication Equipment (DCE): modems, multiplexors, etc

    DCE to DTE requires all lines run straight through
    DTE to DTE usually requires swapping of the following lines

        RD  and TD        RD  and TD
        RTS and CTS    or    RTS,CTS and DCD
        DTR and DSR        DCD and RTS,CTS

%    Signal Functions

    GND    Ground            protective safety ground
    TD     Transmit Data        DTE output data
    RD     Receive Data        DTE input data
    RTS    Request To Send        DTE output, DTE would like to transmit
    CTS    Clear To Send        DTE input, DCE is ready to transmit
    DSR    Data Set Ready        DTE input, DCE is ready to communicate
    SG     Signal Ground        provides a Zero reference voltage
    DCD    Data Carrier Detect  DTE input, data link established, also
                    known as Receive Line Signal Detect (RLSD)
    DTR    Data Terminal Ready  DTE output, device ready
    RI     Ring Indicator        DTE input, announces incoming call


    - RTS/CTS is used for half duplex line turn around
    - in half duplex DCD is asserted only by the receiving device
    - full duplex modems tie CTS & DCD together (no CTS/RTS handshaking)
    - most modems require DTR to be present to respond to commands
    - maximum voltages are between -15 volts and +15 volts
    - binary outputs are between +5 to +15 volts and -5 to -15 volts
    - binary inputs are between +3 to +15 volts and -3 to -15 volts
    - input voltages between -3 to +3 are undefined while output voltages
      between -5 and +5 are undefined
    - positive voltages indicate ON or SPACE, negative voltages indicate
      OFF or MARK