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Text File | 1995-08-27 | 67KB | 1,139 lines

This file includes new knowledge about many Intel processors and their clones. If you're writing system software, then you should read this file. Thank you! (C) Copyright Christian Ludloff (M) 07/1994 Ludwig-Kühn-Straße 15 (P) 01.09.1995 D-09123 CHEMNITZ, Germany (V) 3.1.1 voice +49-(0)371-242091 (?) 80x86.CPU fax +49-(0)371-242091 eMail cl@box.in-chemnitz.de eMail cl@vgasoft.com Fido 2:2426/2240.14 This file is mine! And remember: What's mine is mine! Please, send updates or corrections directly to me and do not modify this file yourself. I will mention your name at the end of the file when adding your new knowledge. That's the only way to fight against xxx versions. Thank you! ============================================================================== The new flags in the EFLAGS register ==================================== ------------------------------------------------------------------------------ bit description ------------------------------------------------------------------------------ 21 CPUID instruction support flag If you can use this bit (set/reset), then your CPU supports the new CPUID instruction. So you must not install a handler for the invalid opcode exception before you execute this new processor instruction. 20 VIP - Virtual Interrupt Pending flag 19 VIF - Virtual Interrupt Flag These two bits are used by the virtual interrupt feature of the V86- enhanced CPUs from Intel. You can use the CPUID instruction to check your processor for the support of this feature. ------------------------------------------------------------------------------ The new Control Register CR4 ============================ This register contains some flag bits to enable or disable the new features. You will find it only on iPentium processors and on some newer Intel CPUs. To find out, whether your CPU contains the CR4 or not, you should use the CPUID instruction (feature flags). If your processor supports the enhanced virtual mode, then it will support at least bit 0 and 1 of CR4 (as the newer i486 do). Don't try to set bits, which are not supported by your CR4 register! ------------------------------------------------------------------------------ bit description ------------------------------------------------------------------------------ 31..7 reserved 6 MCE - enable machine check exception (new; exception #12h) 1=enable the machine check exception 0=disable the machine check exception (like a i486) 5 reserved (for enabling the 36bit-addressing and the 2MB-paging) 4 PSE - enable page size extension 1=enable the 4MB pages 0=disable the 4MB pages (like a i486) 3 DE - enable debugging extension 1=enable the I/O breakpoints (see DR7.R/W) and access to new DR4/DR5 0=disable the I/O breakpoints (like a i486) 2 TSD - enable read time stamp counter instruction 1=enable RDTSC instruction for CPL=0 only 0=enable RDTSC instruction for all CPLs 1 PVI - enable protected mode virtual interrupts 1=enable virtual interrupts in protected mode 0=disable virtual interrupts in protected mode (like a i386) 0 VME - enable virtual mode virtual interrupts 1=enable virtual interrupts in virtual mode 0=disable virtual interrupts in virtual mode (like a i386) ------------------------------------------------------------------------------ The new Probe Mode Control Register =================================== This register is visible through the iPentium ICE (In-Circuit-Emulator) only. ------------------------------------------------------------------------------ bit description ------------------------------------------------------------------------------ 31 SMM (SMM active, read only, similar to former DR6.bit12) 1=SMM is active 0=SMM is not active 30..7 reserved 2 PB1 (performance monitoring or breakpoint monitoring, see MSR #11h.25) 1=pin PM1/BP1 monitors breakpoint #1 matches 0=pin PM1/BP1 monitors performance monitoring counter #1 1 PB0 (performance monitoring or breakpoint monitoring, see MSR #11h.9) 1=pin PM0/BP0 monitors breakpoint #0 matches 0=pin PM0/BP0 monitors performance monitoring counter #0 0 ICEBP (ICEBP enabled, similar to former DR7.bit12) 1=every debug exception activates PRDY and enters the Probe Mode 0=normal behaviour ------------------------------------------------------------------------------ The new R/W-bits in the Debug Register DR7 ========================================== R/W=1-0 - set a breakpoint for I/O accesses (new; but if CR4.DE=0, then reserved like on i386) The GD-bit in the Debug Register DR7 ==================================== The DR7 contains the GD bit too (bit13). This bit is supported on the i386 and the i486 too. If it is set to 1, then any access (read and write) to any Debug register causes the exception #01h. The exception handler is called with GD=0, so that it can access the Debug Registers. This former undocumented bit can be used to crash almost all modern debuggers. But remember: If your own code trys to set the GD bit to 1 and it is always set to 1, then your access to DR7 will cause the exception #01h too! So I don't recommend you to use this bit, if you want your software to run as stable and to be as compatible, as possible! There's only one way, to clear the GD bit and you must be in real mode for the following routine: install your own IDT by loading a new value to the IDTR and create a handler for the exception #01h, which leaves the GD bit in DR7 set to 0 and which returns directly to the code, to re-install the old IDTR value. As you can see, the GD-clearing is not possible (for CPL=3 code) in virtual mode, because you have to install an 'in-complete' exception #01h handler. The new implemented model specific registers MSR #00h-13h ========================================================= Only the iPentium processor contains these new registers. They are 64 bit wide and you must use EDX:EAX to handle them. You will find some MSRs on the newer IBM 386/486SLC processors too. On the new iP6 processor the MSRs are included too, but Intel may have changed their functions. The performance monitoring is now possible for more than two counters at the same time and more events. Here Intel implemented the Machine Check Exception Registers, the new added Test Registers (old TR0-7 don't exist any longer!), the Time Stamp Counter and the two Performance Monitoring Counters #0 and #1 with the Counter Control and Event Selection Register. ------------------------------------------------------------------------------ MSR description (Intel iPentium) ------------------------------------------------------------------------------ 00h MCA - machine check exception address register (read only) This register contains the physical address after a data parity er- ror occured on the CPU bus. This may end up in a machine check ex- ception (#12h), when you enable it via CR4.MCE. bit63..0 ADDRESS (64 bit wide) ------------------------------------------------------------------------------ 01h MCT - machine check exception type register (read only) Describes the type of the bus cycle if a machine check exception oc- cured on your processor's bus. bit63..6 reserved bit5 THERR (1=thermal error, 0=no thermal error ) This bit is set to one, if the cooling fan is removed. The THERR also indicates, if the cooling fan fails (fan state) and the processor is set to 1:1 clock speed ratio (to save power). The CHK bit will not be affected by the THERR bit! bit4 LOCK-state (1=LOCK active, 0=LOCK inactive ) bit3 M/IO-state (1=memory access, 0=I/O access ) bit2 D/C-state (1=data access, 0=code access ) bit1 W/R-state (1=write, 0=read ) bit0 CHK-state (1=MSR #00/01h valid, 0=MSR #00/01h invalid) ------------------------------------------------------------------------------ 02h TR1 - parity reversal test register ('write only') bit63..14 reserved bit13 MC microcode (reverse parity on read) bit12 DTD data TLB data bit11 DTT data TLB tag bit10 DD data cache data (use byte writes for individual access) bit9 DT data cache tag bit8 ITD code TLB data bit7 ITT code TLB tag bit6 ID3 code cache data odd bits (255,253..131,129) bit5 ID2 code cache data even bits (254,252..130,128) bit4 ID1 code cache data odd bits (127,125..3,1) bit3 ID0 code cache data even bits (126,124..2,0) bit2 IT code (instruction) cache tag bit1 NS no shutdown 1=assert IERR# only on parity error 0=assert IERR# and shutdown on parity error bit0 PES parity error summary (read&write, set on any par. err.) Writing a one into bits12..2 reverses the sense of the parity ge- neration for any write into the corresponding array (for normal and for testability accesses). For the microcode bad parity may be for- ced on a read by setting TR1.MC to one. ------------------------------------------------------------------------------ 03h reserved and never implemented by Intel (don't try to read it) ------------------------------------------------------------------------------ 04h TR2 - instruction cache end bit test register (read and write) bit63..4 reserved bit3..0 END BITS These bits indicate instruction boundaries. If the given byte is the last byte in an instruction, the corresponding end bit is set to one. This mechanism aids the decode of two variable length instructions per clock by providing information on where the boundary between instructions is. ------------------------------------------------------------------------------ 05h TR3 - cache data test register (read and write) bit63..32 reserved bit31..0 DATA This is where the data is held on its way into or out of the internal L1-cache. ------------------------------------------------------------------------------ 06h TR4 - cache tag test register (read and write) bit63..32 reserved bit31..8 TAG bit7..3 reserved bit2 LRU 1=points to way #1 0=points to way #0 bit1..0 VALID if TR5.CD=0 (code cache) x-1=cache line valid x-0=cache line invalid if TR5.CD=1 (data cache) 1-1=cache line in M state 1-0=cache line in E state 0-1=cache line in S state 0-0=cache line in I state ------------------------------------------------------------------------------ 07h TR5 - cache control test register ('write only') bit63..15 reserved bit14 WB - selects writeback or writethrough 1=writeback (for that particular line; data cache only) 0=writethrough (for that particular line; both caches) bit13 CD - selects code or data cache 1=data cache 0=code cache bit12 ENTRY - selects one of the two ways in the cache 1=way #1 0=way #0 bit11..5 SET 0..127h - select one of the 128 sets bit4..2 BUFFER 0..7h - select one of the 8 portions of a cache line to be visible through TR3 bit1..0 CONTROL - select the operation 1-1=flush 1-0=testability read 0-1=testability write 0-0=normal operation ------------------------------------------------------------------------------ 08h TR6 - TLB command test register (read and write) bit63..32 reserved bit31..12 LINEAR ADDRESS bit11 V - valid state (valid or invalid TLB entry) 1=valid TLB-entry 0=invalid TLB-entry bit10 D - dirty state (write access made to page; data TLB only) 1=write access was made 0=write access was not made bit9 U - user state (privilege level access allowed) 1=CPL=0 0=CPL=0..3 bit8 W - writeable state (writes allowed; data TLB only) 1=allows writes 0=no writes, read only bit7..3 reserved bit2 PS - selects the page size (data TLB only) 1=4MB pages 0=4KB pages bit1 CD - selects code or data TLB 1=data TLB 0=code TLB bit0 OP - selects the operation 1=TLB read 0=TLB write ------------------------------------------------------------------------------ 09h TR7 - TLB data test register (read and write) bit63..32 reserved bit31..12 PHYSICAL ADDRESS bit11 PCD - page level cache disable bit (paging attribute PCD) bit10 PWT - page level write through bit (paging attribute PWT) bit9 L2 \ bit8 L1 > three LRU bits (entry to be replaced) bit7 L0 / bit6..5 reserved bit4 H - hit indicator (set to 1 during testability writes) 1=input linear address matches a valid entry 0=input linear address don't matches a valid entry bit3..2 ENTRY - select one of the four ways testability write -> way to write testability read -> way that resulted in a read hit bit1..0 reserved ------------------------------------------------------------------------------ 0Ah reserved and not longer implemented by Intel (don't try to read it) Because the iPentium A-step processor was supposed to include a 36bit- addressing and 2MB-paging, there has been the TR8 too. But at the last minute Intel has removed these features and the TR8 from the iPentium. TR8 - TLB data test register (part II) bit63-4 reserved bit3-0 PHYSICAL ADDRESS (A35..A32) ------------------------------------------------------------------------------ 0Bh TR9 - BTB tag test register (read and write) bit63..32 reserved bit31..6 TAG ADDRESS bit5..2 reserved bit1..0 HISTORY ------------------------------------------------------------------------------ 0Ch TR10 - BTB target test register (read and write) bit63..32 reserved bit31..0 TARGET ADDRESS ------------------------------------------------------------------------------ 0Dh TR11 - BTB control test register (read and write) bit63..12 reserved bit11..6 SET 0..63h - select one of the 64 sets to access bit5..4 reserved bit3..2 ENTRY - select a way 0..3h - select one of the four ways within the set bit1..0 CONTROL - select the operation 1-1=flush 1-0=testability read 0-1=testability write 0-0=normal operation ------------------------------------------------------------------------------ 0Eh TR12 - new feature control register ('write only') bit63..10 ? reserved bit9 ITR interrupt priority 1=enable I/O instruction restart feature for the SMM and change the interrupt priority 0=disable I/O instruction restart feature for the SMM and use the standard interrupt priority See Pentium Family User's Manual volume #1 (data book) table 19-2 for some details. This bit should be suppor- ted only on the iP54C models with the new added I/O in- struction restart feature for the SMM. bit8 fTR fast tracing (see TR12.TR too) 1=CPU generates fast branch-trace-message bus-cycles 0=CPU don't generates fast branch-trace-message bus- cycles The fast tracing feature should exist only on such Pen- tium processors working with different ex- and internal speeds (like the new iP54C model). So the new fast mes- sages produce only the second bus-cycle. bit7 ? unknown (but used!) bit6 AHD auto halt disable (iP54C only) 1=auto halt feature disabled 0=auto halt feature enabled bit5 ? unknown bit4 AD APIC disable (iP54C B-step with integrated APIC only) 1=internal APIC disabled 0=internal APIC enabled To re-enable the APIC, a warm reset of the part must be performed, after clearing this bit. bit3 CI cache inhibit 1=internal L1-cache disabled (L2-cache unchanged) 0=internal L1-cache enabled (L2-cache unchanged) bit2 SE single pipe execution 1=v-pipeline disabled and not used 0=both pipelines enabled and used bit1 TR tracing 1=CPU generates branch-trace-message bus-cycles for the external execution control 0=CPU don't generates the branch-trace-message bus- cycles bit0 NBP no branch prediction 1=BTB not used (then a move to CR3 disables BTB use!) 0=BTB used to predict branches ------------------------------------------------------------------------------ 0Fh reserved and never implemented by Intel (don't try to read it) ------------------------------------------------------------------------------ 10h time stamp counter (read and write) This counter counts the internal CPU clock cycles since the last re- set. It has a capacity of about 5850 years when you have a 100 MHz processor. You can read the value via the RDTSC / RDMSR instruction. bit63..0 time stamp counter value (64 bit wide, read/write) ------------------------------------------------------------------------------ 11h counter event selection and control register (read and write) This register controls the two internal counters #0 and #1. They can be programmed to count about 40 different events. bit63..32 reserved (for two more counters in future models?) bit31..26 reserved bit25 external pin PM1 selection 1=pin shows counter overflows 0=pin shows counter increments bit24 counter type for counter #1 1=count clock cycles only 0=count events bit23 enable counting in CPL=3 for counter #1 1=enable counting when CPL=3 ('count user software') 0=disable counting when CPL=3 bit22 enable couning in CPL=2..0 for counter #1 1=enable counting when CPL=2..0 ('count system overhead') 0=disable counting when CPL=2..0 bit21..16 event type to count with counter #1 (see list below!) bit15..10 reserved bit 9 external pin PM0 selection 1=pin shows counter overflows 0=pin shows counter increments bit8 counter type for counter #0 1=count clock cycles only 0=count events bit7 enable counting in CPL=3 for counter #0 1=enable counting when CPL=3 ('count user software') 0=disable counting when CPL=3 bit6 enable counting in CPL=2..0 for counter #0 1=enable counting when CPL=2..0 ('count system overhead') 0=disable counting when CPL=2..0 bit5..0 event type to count with counter #0 (see list below!) ------------------------------------------------------------------------------ 12h counter #0 (read and write) bit63..40 reserved bit39..0 counter #0 value (40 bit wide) ------------------------------------------------------------------------------ 13h counter #1 (read and write) bit63..40 reserved bit39..0 counter #1 value (40 bit wide) ------------------------------------------------------------------------------ >13h reserved and not implemented by Intel (don't try to read them) ------------------------------------------------------------------------------ The IBM 386/486SLC processors include the following Model Specific Registers: ------------------------------------------------------------------------------ MSR description (IBM 386/486SLC and IBM 486BL3 'Blue Lightning') ------------------------------------------------------------------------------ 1000h processor operation register (IBM 386/486SLC) bit63..19 reserved bit18 low power PLA mode (IBM 486SLC only?) 1=power down additional dynamic parts during halt-state 0=don't power down these parts during low-power halt-state bit17 factory read testing (IBM 486SLC only?) 1=force all reads from ext. memory, even if cache is on 0=don't force all reads from external memory bit16 factory internal cache parity testing (IBM 486SLC only?) 1=use odd parity (generates a cache parity error) 0=use even parity (normal operation) bit15 enable cacheability of floating point operand reads 1=boosts performance, if an external Cyrix FPU is used 0=normal operation (if an external Intel FPU is used!!!) bit14 switch the ERROR input line... 1=...to a hidden memory address strobe output line You can set this bit only at the first WRMSR after a CPU reset. Further attempts at changing the bit are ignored! 0=...to the ERROR input pin to Intel compatible ERROR bit13 low power halt mode (HLT instruction: stops internal clock) 1=enable low power halt mode 0=disable low power halt mode bit12 wait for READY after output 1=the processor waits until READY is active after all out- put instructions, before executing the next instruction 0=don't wait for READY bit11 cache reload status (set, when internal cache reload occurs) bit10 internal L1-cache enable set source 1=use MSR #1001h for the limits set You can set this bit only at the first WRMSR after a CPU reset. Further attempts at changing the bit are ignored! 0=use external hardware line input bit9 disable cache lock mode 1=allows the CPU to recognize the locked read-modify-write cycle, but does not cache the line 0=normal operation bit8 reserved for unknown function or unused bit7 enable internal L1-cache 1=enable internal L1-cache 0=disable internal L1-cache bit6 disable caching for E0000h to E0FFFh (4K) 1=disable caching (if Double Byte Character Support used) 0=enable caching (if DBCS not used on japanes systems) bit5 enable power interrupt PWI 1=enable power interrupt PWI 0=disable power interrupt PWI bit4 enable flush snooping 1=enable flush snooping (can be used, if bit3=0) 0=disable flush snooping bit3 enable snoop input 1=enable snoop input 0=disable snoop input bit2 enable A20 mask 1=line A20 disabled, unless paging is active (see CR0.PG) 0=external control or entire address range is accessable bit1 enable cache parity 1=if a parity error occurs, then the internal L1-cache is flushed, disabled (bit7=0), the flag is set (bit0=1) and cache parity is disabled (bit1=0); NMI handler is called 0=disable cache parity bit0 parity error occured 1=parity error occured (even, if bit1=1 -> no action) 0=no parity error occured (set bit0=0 to clear this flag) ------------------------------------------------------------------------------ 1001h cache region control register (IBM 386/486SLC) bit63-48 reserved bit47-32 extended memory cache limit number of 64K blocks starting at the 1M boundary, that can be cached (so 0Fh means 15MB are cacheable...) bit31-16 read only cache blocks each bit represents a 64K region in the 1st MB, that has a ROM memory (bit31=1 -> ROM at F000h...), a write into area marked as ROM will not be updated in cache memory bit15-0 first 1MB cacheable each bit represents a 64K region in the first MB, that can be cached (bit15=1 -> cache F000h ... bit0=1 -> cache 0h) ------------------------------------------------------------------------------ 1002h processor operation register 2 (not on IBM 386SLC) bit63-30 reserved bit29 enable external dynamic frequency shift 1=enable external dynamic frequency shift 0=disable external dynamic frequency shift bit28 dynamic frequency shift ready 1=CPU is ready for the shift (requested by hardware or by setting bit27=1) -> clock can be changed 0=CPU is not ready for the shift bit27 dynamic frequency shift request 1=request the CPU to prepare for a clock input frq. change 0=normal operation bit26-24 clock mode 000=divide incoming clock by 2 (same as i386SX) 011=use the incoming clock; make no divide; used for doub- ling the internal CPU speed 100=3:1 clock mode bit23-0 reserved ------------------------------------------------------------------------------ 1004h processor control register (at least IBM 486BL3) bit63-24 reserved bit23 OS/2 boot 0=for DD1-hardware 1=for DD0-hardware: for OS/2 boot bit22 MOV CR0 decode 0=for DD0-, DD1A-, DD1B-, DD1D-hardware 1=for DD1C-hardware bit21 reserved bit20 cache low power 0=DD0: ever, DD1: cache stays on 1=DD1: disable cache when not in use bit19 reserved bit18 NOP 0=DD0: NOP=2 cycles, DD1: NOP=3 cycles 1=DD0: NOP=3 cycles, DD1: NOP=2 cycles bit17 NA16 (bus pipelining for 16 bit) bit16-5 unknown bit4 MOVS split bit3 power saving cache feature bit2 reserved bit1 enable MOV CRx decode (DD1B, DD1C: reserved) bit0 reserved ------------------------------------------------------------------------------ Some MSRs could exist on every ≥386 CPU. They are used by the vendor during a test at the factory. I wish you a happy searching. But if you find one, you're not able to use it, before you know it's structure. Send me the no., please! The events for the two iPentium counters #0 and #1 ================================================== ------------------------------------------------------------------------------ bits no description ------------------------------------------------------------------------------ 000000 00h data reads 000001 01h data writes 000010 02h data TLB misses 000011 03h data read misses 000100 04h data write misses 000101 05h writes (hits) to M or E state lines 000110 06h data cache lines written back 000111 07h external snoops 001000 08h data cache snoop hits 001001 09h memory accesses in both pipes 001010 0Ah bank conflicts 001011 0Bh misaligned data memory references 001100 0Ch code reads 001101 0Dh code TLB misses 001110 0Eh code cache misses 001111 0Fh any segment register loaded 010000 10h segment descriptor cache accesses 010001 11h segment descriptor cache hits 010010 12h branches 010011 13h BTB hits 010100 14h taken branches or BTB hits 010101 15h pipeline flushes 010110 16h instructions executed in both pipes 010111 17h instructions executed in the v-pipe 011000 18h clocks while bus cycle in progress (bus utilization) 011001 19h pipe stalled by full write buffers (writes backup) 011010 1Ah pipe stalled by waiting for data memory reads 011011 1Bh pipe stalled by writes to M or E lines 011100 1Ch locked bus cycles 011101 1Dh I/O read or write cycles 011110 1Eh non-cacheable memory references 011111 1Fh pipeline stalled by address generation interlock 100000 20h unknown, but counts 100001 21h unknown, but counts 100010 22h floating-point operations 100011 23h breakpoint matches on DR0 register 100100 24h breakpoint matches on DR1 register 100101 25h breakpoint matches on DR2 register 100110 26h breakpoint matches on DR3 register 100111 27h hardware interrupts 101000 28h data reads or data writes 101001 29h data read misses or data write misses 2Ah..3Fh reserved and unused (no counting) ------------------------------------------------------------------------------ At the moment it seems, that Intel has changed/enhanced this list for the iP6! The new instructions ==================== i486: The newer processors with "&" printed on the package will support the CPUID-flag in EFLAGS, the CPUID instruction, the CR4 register bits1/0 and instructions for access to the CR4 register, the enhanced virtual mode, the system management mode SMM and the RSM instruction. The new i486DX2WB processor supports the 4MB-pages too. If this CPU runs with writeback mode, then the CPUID value is '0470'. If it is running with writethrough mode, then you receive the value '0436'. The real mask- revision (stepping) you will get only after the processor reset! Pentium: The iPentium processors support all the news listed above and the new instructions listed below. UMC,AMD: The UMC U5S, the UMC U5D and the AMD enhanced DX2/DX4 processors sup- port the CPUID-flag in EFLAGS and the CPUID instruction. IBM: The IBM 386/486SLC and the IBM 486BL3 'Blue Lightning' processors are supporting some MSRs (see above) and the instructions to use them. ------------------------------------------------------------------------------ name opcodes description ------------------------------------------------------------------------------ CPUID 0F A2 CPU identification in: EAX=0 get max. identification level and vendor out: EAX=1 max. identification level is 1 now EBX-EDX-ECX vendor identification 'GenuineIntel' - Intel i486, iPentium or iP6 CPU 'UMC UMC UMC ' - UMC U5S or U5D processor 'AuthenticAMD' - AMD 486DX2 or DX4 (enh.) processor 'CyrixInstead' - Cyrix M1 processor in: EAX=1 get chip type and the supported features out: EAX=0:TFMS CPU type (type, family, model, stepping) type The type is encoded in the bits13/12. 00=1st dual iPentium CPU (iP54C) 01=iPentium OverDrive processor 10=2nd dual iPentium CPU (iP54C) 11=reserved family 4=486, 5=iPentium, 6=iP6 model Intel486: 0=DX, 1=DX50, 2=SX, 3=DX2, 4=SL, 5=SX2, 7=DX2WB, 8=DX4 UMC486: 1=U5D, 2=U5S AMD486: 3=DX2, 7=DX2WB, 8=DX4, 9=DX4WB iPentium: 0=5V-60/66 MHz A-step chips, 1=5V-60/66 MHz, 2=3.3V-75/90/ 100/120/133MHz, 3=P24T, 4=OvDr for iPentium-3.3V, 5=OvDr for iDX4, 6=OvDr for iPentium-5V iP6: 4=P55CT (iPentium-3.3V OvDr) stepping steppings sometimes cover several masks comment iPentium-5V: no fDIVbug since step no.7 iPentium-3V: no fDIVbug since step no.4 EDX=flags supported features (i486, iPentium, iP6) bit31..10 reserved (=0) bit9=1 CPU contains a local APIC (iPentium-3V) bit8=1 CMPXCHG8B instruction supported bit7=1 machine check exception supported bit6=0 reserved (36bit-addressing & 2MB-paging) bit5=1 iPentium-style MSRs supported bit4=1 time stamp counter TSC supported bit3=1 page size extensions supported bit2=1 I/O breakpoints supported bit1=1 enhanced virtual 8086 mode supported bit0=1 CPU contains a floating-point unit (FPU) info: can be used in all CPLs; serializes the pipelines; the first iPentiums did not supported several CPUID levels and they show EAX=FMS and EBX-EDX-ECX=vendor only! (so they seem to provide more than 500h CPUID levels) ------------------------------------------------------------------------------ RDMSR 0F 32 read a model specific register value in: ECX number of the MSR (0..13h on the iPentium) out: EDX:EAX value of the MSR (64 bit wide) clks: 20-24 (iPentium) info: instruction can only be used when CPL=0 (but many EMMs do allow the usage from CPL>0 without problems; if the instruction is used in a Windows 3.1 DOS-box, then the DOS-session will be 'crashed' due to an opcode error) ------------------------------------------------------------------------------ WRMSR 0F 30 write a value to a model specific register in: ECX number of the MSR (0..13h on the iPentium) EDX:EAX value (64 bit wide) clks: 30-45 (iPentium) info: instruction can only be used when CPL=0 (but some EMMs like QEMM 7.04 do allow the usage from CPL>0) ------------------------------------------------------------------------------ RDTSC 0F 31 read time stamp counter value out: EDX:EAX time stamp counter value (64 bit wide) clks: 6 (iPentium, CPL=0), 11 (iPentium, CPL=1-3) info: instruction can be disabled for CPL=1..3 via CR4.TSD ------------------------------------------------------------------------------ CMPXCH8B 0F C7 compare & exchange 64 bits, similar to CMPXCHG RSM 0F AA resume from system management mode (only in SMM!) MOV EAX,CR4 0F 20 E0 read the CR4 register value MOV CR4,EAX 0F 22 E0 write a value to the CR4 register ------------------------------------------------------------------------------ The MOV EAX,TRxh and MOV TRxh,EAX instructions are not longer supported by the iPentium processors, because the Test Registers were placed into the MSRs. The iPentium stepping values ============================ Intel Pentium P5 processor ------------------------------------------------------------------------------ type family model step mask clock SX-no Vcc in V °C note ------------------------------------------------------------------------------ 0 5 1 3 B1 50/50 Q0399 4.75-5.25 85 1,2 0 5 1 3 B1 60/60 Q0352 4.75-5.25 85 1 0 5 1 3 B1 60/60 Q0400 4.75-5.25 75 1,2 0 5 1 3 B1 60/60 Q0394 4.75-5.25 80 2,3 0 5 1 3 B1 66/66 Q0353 4.90-5.25 75 1 0 5 1 3 B1 66/66 Q0395 4.90-5.25 70 2,3 0 5 1 3 B1 60/60 Q0412 4.75-5.25 85 1 0 5 1 3 B1 60/60 SX753 4.75-5.25 85 1 0 5 1 3 B1 66/66 Q0413 4.90-5.40 75 1 0 5 1 3 B1 66/66 SX754 4.90-5.40 75 1,4 ------------------------------------------------------------------------------ 0 5 1 5 C1 60/60 Q0466 4.75-5.25 80 3 0 5 1 5 C1 60/60 SX835 4.75-5.25 80 3 0 5 1 5 C1 66/66 Q0467 4.90-5.40 70 3 0 5 1 5 C1 66/66 SX837 4.90-5.40 70 3 ------------------------------------------------------------------------------ 0 5 1 7 D1 60/60 Q0625 4.75-5.25 80 3 0 5 1 7 D1 60/60 SX948 4.75-5.25 80 3 0 5 1 7 D1 60/60 SX974 5.15-5.40 70 3 0 5 1 7 D1 66/66 Q0626 4.90-5.40 70 3 0 5 1 7 D1 66/66 SX950 4.90-5.40 70 3 0 5 1 7 D1 66/66 Q0627 5.15-5.40 70 3 0 5 1 7 D1 66/66 SX949 5.15-5.40 70 3 ------------------------------------------------------------------------------ 1: non-heat spreader package 2: engineering samples only 3: heat spreader package 4: 66 MHz B1 shipped after work week 34 of 1993 were tested to Vcc=4.90-5.40V Intel Pentium P54 processor ------------------------------------------------------------------------------ type family model step mask clock SX-no comment ------------------------------------------------------------------------------ 0 5 2 1 B1 75/50 Q0540 ES 0 5 2 1 B1 75/50 Q0541 ES 0 5 2 1 B1 90/60 Q0542 STD 0 5 2 1 B1 90/60 Q0613 VR 0 5 2 1 B1 90/60 Q0543 DP 0 5 2 1 B1 100/66 Q0563 STD 0 5 2 1 B1 100/66 Q0587 VR 0 5 2 1 B1 100/66 Q0614 VR 0 5 2 1 B1 75/50 Q0601 TCP 0 5 2 1 B1 90/60 SX879 STD 0 5 2 1 B1 90/60 SX885 MD 0 5 2 1 B1 90/60 SX909 VR 0 5 2 1 B1 90/60 SX874 DP,STD 0 5 2 1 B1 100/66 SX886 MD 0 5 2 1 B1 100/66 SX910 VR,MD ------------------------------------------------------------------------------ 0 5 2 2 B3 90/60 Q0628 STD 0/2 5 2 2 B3 90/60 Q0611 STD 0/2 5 2 2 B3 90/60 Q0612 VR 0 5 2 2 B3 100/66 Q0677 VRE,MD 0 5 2 2 B3 75/50 Q0606 TCP 0 5 2 2 B3 75/50 SX951 TCP 0 5 2 2 B3 90/60 SX923 STD 0 5 2 2 B3 90/60 SX922 VR 0 5 2 2 B3 90/60 SX921 MD 2 5 2 2 B3 90/60 SX942 DP,STD 2 5 2 2 B3 90/60 SX943 DP,VR 2 5 2 2 B3 90/60 SX944 DP,MD 0 5 2 2 B3 100/66 SX960 VRE,MD ------------------------------------------------------------------------------ 0/2 5 2 4 B5 75/50 Q0704 TCP 0/2 5 2 4 B5 75/50 Q0666 STD 0/2 5 2 4 B5 90/60 Q0653 STD 0/2 5 2 4 B5 90/60 Q0654 VR 0/2 5 2 4 B5 90/60 Q0655 MD 0/2 5 2 4 B5 100/66 Q0656 MD 0/2 5 2 4 B5 100/66 Q0657 VR,MD 0/2 5 2 4 B5 100/66 Q0658 VRE,MD 0/2 5 2 4 B5 120/60 Q0707 VRE,MD,max.60°C 0/2 5 2 4 B5 120/60 Q0708 STD,max.60°C 0/2 5 2 4 B5 75/50 SX975 TCP 0/2 5 2 4 B5 75/50 SX961 STD 0/2 5 2 4 B5 90/60 SX957 STD 0/2 5 2 4 B5 90/60 SX958 VR 0/2 5 2 4 B5 90/60 SX959 MD 0/2 5 2 4 B5 100/66 SX962 VRE,MD ------------------------------------------------------------------------------ 0/2 5 2 5 C2 75/50 Q0725 TCP 0/2 5 2 5 C2 75/50 Q0700 STD 0/2 5 2 5 C2 75/50 Q0749 MD 0/2 5 2 5 C2 90/60 Q0699 STD 0/2 5 2 5 C2 100/50,66 Q0698 VRE,MD 0/2 5 2 5 C2 100/50,66 Q0697 STD 0/2 5 2 5 C2 120/60 Q0711 VRE,MD 0/2 5 2 5 C2 120/60 Q0732 VRE,MD 0/2 5 2 5 C2 133/66 Q0733 MD 0/2 5 2 5 C2 133/66 Q0751 MD 0/2 5 2 5 C2 133/66 Q0775 VRE,MD 0/2 5 2 5 C2 75/50 SK079 TCP 0/2 5 2 5 C2 75/50 SX969 STD 0/2 5 2 5 C2 75/50 SX998 MD 0/2 5 2 5 C2 90/60 SX968 STD 0/2 5 2 5 C2 100/50,66 SX970 VRE,MD 0/2 5 2 5 C2 100/50,66 SX963 STD 0/2 5 2 5 C2 120/60 SK086 VRE,MD 0/2 5 2 5 C2 120/60 SX994 VRE,MD 0/2 5 2 5 C2 133/66 SK098 MD 0/2 5 2 5 C2 133/66 SK103 VRE,MD ------------------------------------------------------------------------------ 0/2 5 2 5 mA1 75/50 Q0686 TCP 0/2 5 2 5 mA1 75/50 Q0689 SPGA 0/2 5 2 5 mA1 90/60 Q0694 TCP 0/2 5 2 5 mA1 90/60 Q0695 SPGA 0/2 5 2 5 mA1 75/50 SK089 TCP 0/2 5 2 5 mA1 75/50 SK091 SPGA 0/2 5 2 5 mA1 90/60 SK090 TCP 0/2 5 2 5 mA1 90/60 SK092 SPGA ------------------------------------------------------------------------------ STD : Vcc=3.135-3.465V DP : dual processor VR : Vcc=3.300-3.465V MD : modified timing VRE : Vcc=3.450-3.600V ES : engineering sample TCP : TCP package mA1-step : voltage reduction technology for SPGA : SPGA package Pentium 75 and 90 MHz processors Intel Pentium OverDrive P24T processor ------------------------------------------------------------------------------ type family model step mask clock SX-no comment ------------------------------------------------------------------------------ 1 5 3 1 B1 63/25 SZ953 version 1.0 1 5 3 1 B2 63/25 SZ990 version 1.0 ------------------------------------------------------------------------------ The (known) iPentium bugs ========================= ------------------------------------------------------------------------------ P5 P54C P24T BCD BBBCA BB <- masks for P5: B1,C1,D1 / P54C: B1,B3,B5,C2,mA1 / P24T: B1,B2 111 13521 12 errata descriptions, see Intel order #242480-005 for all details ------------------------------------------------------------------------------ x BOFF# hold timing x incomplete initialization may flush the internal pipeline x IV pin may not be asserted under certain conditions x testability writes to data TLB may store wrong parity x LRU bits in the data cache TLBs are updated incorrectly x a replacement writeback cycle may invade a locked seqeunce x RUNBIST instruction generates incorrect BIST signature xx data breakpoint mistakenly remembered on a faulty instruction xxx RESET affects RUNBIST instruction execution in boundary scan xx xxx xx locked operation during instruction exec tracing may hang CPU xx xxx xx BP or single-step may be missed for one instruction after STI xx internal snoop problem due to reflection on address bus xx internal parity error on uninitialized data cache entry xx xxx xx missing shutdown after an IERR# xx x processor core may not serialize on bus idle xx xxx SMIACT# assertion during replacement writeback cycle xxx xxx overflow undetected on some number on FIST xxx xxx six operands result in unexpected FIST operation xx x snoop with table-walk violation may not invalid. snooped line xx xx FDIV bug (Intel: 'slight precision loss') xxx power-up BIST failure xxx xxx xx FLUSH#, INIT or MCE dropped due to floating-point exception xxx xxxxx xx floating point operations may clear alignment check bit (AC) xxx xxxxx xx CMPXCHG8B accross page boundary may cause invalid opcode exc. xxx xxx xx single step debug exception breaks out of HALT xxx xxxxx xx EIP altered after specific FP oper. followed by MOV Sreg,Reg xxx xxxxx xx WRMSR into illegal MSR does not generate GP fault xxx xxx xx inconsist. data cache state from concurr. snoop/memory write xxx xx no I/O restart during single-stepping or data BP exceptions xxx xx NMI or INIT in SMM with I/O restart during single-stepping xxx xx SMI# and FLUSH# during shutdown xxx xx FLUSH# with a breakpoint pending causes false DR6 values xxxxx xx STPCLK# deassertion not recognized for 5 CLKs after BRDY# xxx future Pentium OvDr CPU FERR# contention in 2-socket systems x code cache lines not invalidated if snooped on AutoHALT/stop x STPCLK# assertion during HALT instruction hangs system xxxxx xx NMI or INIT during HALT within SMM causes bus activity xxxxx RUNBIST restrictions when run through boundary scan circuitry xxxx FRC mode miscompare due to uninitialized internal register xxxxx xx STPCLK# restrictions during EWBE# xxx xx multiple allocations into branch target buffer xxx 100 MHz REP MOVS speed path xxx xx branche trace message corruption in slow trace mode xxxx FRC lock-step failure during APIC write xxxxx BE4#-BE0# sampled incorrectly at Min Vih xxxx incorrect PCHK# output during boundary scan if in DP mode xxx BE3#-BE0# not driven during boundary scan if RESET high xx BIST disabled xx maximum Icc usage xx CLK required for UP# to be driven ------------------------------------------------------------------------------ ### problem with external snooping while 2 cycles are pending on bus ### STPCLK# assertion and the stop grant bus cycle ### external snooping with AHOLD asserted may cause CPU to hang ### address parity check not supported in dual processing mode ## inconsistent cache state from interCPU pipelined READ -> WRITE ### processors hang during zero WS, pipelined bus cycles ### bus lock-up problem in a specific dual processing mode sequence #### incorrect assertion of PHITM# without PHIT# #### double issuance of read cycles #### line invalidation may occur on read or prefetch cycles #### EADS# or floating ADS# may cause extra invalidates #### HOLD & BOFF# during APIC cycle may cause DP arbitration problem #### system hang after hold during local APIC 2nd INTA cycle ------------------------------------------------------------------------------ +++ remote read message shows valid status after a checksum error +++ change of clearing an unread error in the error register +++ writes to error register clear register +++ three interrupts of the same priority cause lost local interrupt +++ APIC bus synch lost due to checksum error on remote read message +++ HOLD during READ from local APIC register causes incorrect PCHK# +++ HOLD during outstanding interCPU pipelined APIC cycle hangs CPU +++ PICCLK reflection may cause an APIC checksum error ++++ spurious interrupt in APIC through local mode +++ pot. for lost interrupts while using APIC in through local mode ++++ back to back assertions of HOLD may cause lost APIC write cycle ------------------------------------------------------------------------------ * CPU may not reset correctly due to floating FRCMC# pin * ** BRDY# does not have buffer selection capability ------------------------------------------------------------------------------ x : error exists in this mask revision # : dual processing related errata + : APIC related errata * : 75 MHz TCP related errata The RESET-EDX-CPUID-method ========================== All the ≥i386 processors will show their CPUID value after the processor reset in the DX register. Sometimes the value seems to be stored in the high part or in both, the high and the low part of the EDX register. This shift is done by some BIOS versions (probably to save the value during the power on self test). You can get access to the EDX-after-reset-value via generating a processor re- set using the triple-fault-method or the keyboard-controller-reset-method. The reset test will only be useable when running under real mode! On the iPentium processor there are two different resets: the standard and the fast reset (only two clock cycles, without erasing caches...). I sometimes re- ceived a hang-up on the iPentium-60 I checked my reset-software on. Please, remember, that this reset test will not work with all BIOS versions!!! ------------------------------------------------------------------------------ some register values after a processor reset ------------------------------------------------------------------------------ EAX processor is okay, if zero (if not, then contact me and the vendor) EDX value like the CPUID instruction xFMS value 386-xFMS 03xx=i386DX, 13xx=i376?, 23xx=i386SX/CX/EX, 033xx=i376, 034x=iRapidCAD, 43xx=i386SL 486-xFMS A3xx=IBM386SLC, A41x=IBM486SLC, A42x=IBM486SLC2, 84xx=IBM486BLC3 0005=CyrixM5, 0006=CyrixM6, 0007=CyrixM7 586-xFMS 15xC=NexGen Nx586 (similar to iPentium, 1=OverDrive?, C=C-mask?) family 04=i486, 05=iPentium, 06=iP6 model i486: 0=DX, 1=DX50, 2=SX, 3=DX2, 4=SL, 5=SX2, 7=DX2WB, 8=DX4 iPentium: 0/1=5V-60/66 MHz, 2=3V-75/90/100/120/133 MHz, 3=P24T, 4=OvDr for iP5-3.3V, 5=OvDr for iDX4, 6=OvDr for iP5-5V stepping steppings sometimes cover several masks ------------------------------------------------------------------------------ Known 386/486 processor mask revisions ====================================== ------------------------------------------------------------------------------ CPU known mask revisions for the RESET-EDX-CPUID stepping value ------------------------------------------------------------------------------ i386SX 4=A0, 5=B, 6=C?, 8=C-E, 9=D i386CX/EX 9=A i386DX 0=A, 3=B0-B10, 5=D0, 8=D1-D2 i386SL 10=A0-A3, 11=B0-B1 iRapidCAD 0=A i376 5=A, 8=B ------------------------------------------------------------------------------ AMD386SX 5=A, 8=B AMD386DX 5=A, 8=B ------------------------------------------------------------------------------ i486DX25/33 0=A0-A1, 1=B2-B6, 2=C0, 3=C1, 4=D0 i486DX50 0=cA2-cA3, 1=cB0-cB1 i486SL 0=A i486DX2 2=A0-A2, 3=B1, 5=C i486SX 0=A0, 2=B0, 7=cA0, 8=cB0, 3=D, A=E ------------------------------------------------------------------------------ Used 'short-cuts' ================= i386 Intel 80386 processor (i386SX/CX/EX, i386DX) i486 Intel 80486 processor (i486SX, i486SX2, i486DX, i486DX2(WB), i486DX4) iP5 Intel Pentium processor (with 60 or 66 MHz clock) iP54x Intel Pentium processor (with 75, 90, 100, 120, 133 MHz clock) iP55CT Intel P6 OverDrive processor This is a true iP6 processor, which fits into an iPentium-133 socket no.7 (specification 2). It provides 66 MHz external clock speed. The internal clock speed can be 2,5x or 3x as fast. To insert this P55CT into an iPentium-board you need a BIOS-update (FLASH), because there are some slight differences between the P54 and the P55CT. iP6 Intel P6 processor (with 120, 133 MHz clock) iP24D Intel 80486DX2WB processor This is the new i486DX2 with an integrated 8 KB writeback cache. iP24T Intel Pentium OverDrive processor This is the new overdrive for an i486-ZIF-socket II or III including 2x16 KB cache, 32 bit bus, clock 'doubling' (63/25, 83/33 MHz). This CPU has an integrated cooling solution with a fan. Remember that not all boards will work with this processor - sometimes you may get the complete destruction of the CPU as an upgrade result. At the moment the i486DX4-100 is the better and faster (than 63/25 part) solution! chipsets from Intel: Mercury, Saturn, Neptune, Triton and Orion Nx586 This is the NexGen586 processor. It has iPentium-like structures. This CPU has been created as a competitor for the iPentium processor. There are the following technical parameters: 33 MHz external and 2.5x33 MHz internal clock speed; no FPU (there will be a Nx587 part including the FPU which replaces the Nx586); integrated L2-cache controller; 3.3V; a i386 compatible core (no enhanced virtual mode, MSRs and so on); a L1- cache with 2x16 KB; features like branch prediction, register renaming and data forwarding or speculative execution; a 463 pin PGA package; a 0.5µ CMOS technology. The Nx586VL chipset has been created to use this processor in an environment with Vesa Local Bus (VLB). This processor will not fit in the original iPentium socket and it is not compatible to the iPentium by internal (programming) details, but by the speed! NexGen processor detection example (check for i386 compatibility 1st!) is_a_386: MOV AX,5555h ; To detect the NexGen processor, first do set_zero: XOR DX,DX ; check, whether it is an i80386 compatible MOV CX,2h ; processor, or not. If it is a 32 bit CPU, DIV CX ; then execute the division, which changes JNZ no_NexGen ; zero flag on non-NexGen processors. Only JZ is_NexGen ; the NexGen will not change the zero flag. This test routine is based on the original NexGen processor detection. K86 AMD processor with an architecture, similar to the Intel iP6 compareable to the iPentium-120/133 by the speed (130 MIPS) M5 Cyrix Cx80486S(2), Cx80486D(2), Cx80486S(2)-V, Cx80486D(2)-V processor M6 Cyrix Cx80486DX, Cx80486DX-V processor M7 Cyrix Cx80486DX2, Cx80486DX2-V processor M1 Cyrix processor with an architecture, similar to the Intel iP6 compareable to the iPentium-120/133 by the speed (130 MIPS) M1sc Cyrix M1 processor, designed for the 486DX4 socket ('Cyrix 5x86 CPU') compareable to the iPentium-75 by the speed CPL actual Code Privilege Level (0..2=system, 3=user) When running under real mode you are at CPL=0. If you use a memory ma- nager like EMM386, WIN/3, QEMM or 386MAX, then the manager is running at CPL=0 and your DOS-session/-box runs with CPL=3. CRx Control Register x DRx Debug Register x TRx Test Register x MSR Model Specific Register (64 bit wide) TSC Time Stamp Counter (64 bit wide) TLB Translation Lookaside Buffer (≥i486) BTB Branch Target Buffer (≥iPentium) Used sources ============ ------------------------------------------------------------------------------ Pentium Family User's Manual vol.#1, Intel 1994, ISBN 1-55512-225-6 Pentium Family User's Manual vol.#2, Intel 1994, ISBN 1-55512-226-4 Pentium Family User's Manual vol.#3, Intel 1994, ISBN 1-55512-227-2 Optimizations for Intel's 32-Bit Processors, Intel, order number 2411799-001 Pentium Processor Specification Update, 6/95, Intel, order number 242480-005 ------------------------------------------------------------------------------ Hans-Peter Messmer, Pentium, Addison-Wesley 1994, ISBN 3-89319-630-7 Hans-Peter Messmer, PC-Hardwarebuch, Addison-Wesley 1995, ISBN 3-89319-710-9 Ross P. Nelson, 80386/486, Microsoft Press, ISBN 3-86063-200-0 A. Schulman, Undocumented DOS 2nd ed., Addison-Wesley 1994, ISBN 0-201-63287-X Frank van Gilluwe, Undocumented PC, Addison-Wesley 1994, ISBN 0-201-62277-7 ------------------------------------------------------------------------------ Mike Schmit, Optimizing Pentium Code, Dr. Dobbs 1/94 p.40 - about the iPentium Terje Mathisen, Pentium Secrets, BYTE 7/94 p.191 - about the iPentium Georg Schnurer, Noch'n Gedicht, c't 9/94 p.27 - about the UMC U5S Andreas Stiller, Kontrapunkt, c't 11/94 p.79 - about the Nx586 Christian Ludloff, Zwischen den Zeilen, c't 11/94 p.266 - about the iPentium Andreas Stiller, Schwindel entlarvt, c't 12/94 p.62 - some CPUID models Christian Ludloff, Wundersame Wandlung, c't 02/95 p.242 - about the iPentium Andreas Stiller, Intels Antwort, c't 03/95 p.66 - some CPUID models Andreas Stiller, Prozessorgeflüster, c't 04/95 p.26 - some CPUID models Georg Schnurer, Discovery 6, c't 04/95 p.120 - about the new iP6 Georg Schnurer, Wider den Flaschenhals, c't 04/95 p.132 - about the iPentium Andreas Stiller, Prozessorgeflüster, c't 05/95 p.34 - about the Cyrix M1 Andreas Stiller, Prozessorgeflüster, c't 06/95 p.26 - about the Cyrix M1 Andreas Stiller, Waschzettel, c't 07/95 p.186 - about masks & bugs Alex Wolfe, Pentium secrets revealed, EE Times 7/3/95 p.1 - about 4p_v302.zip Alex Wolfe, Embedded Insights, EE Times 7/10/95 p.43 - about 4p_v302.zip Andreas Stiller, Prozessorgeflüster, c't 08/95 p.24 - about the iP55CT ------------------------------------------------------------------------------ software package thanks for INFO.EXE SimCity2000 game CPUID MFT.EXE QEMM v7.04 memory manager CPUID, Performance Monitoring QEMM.SYS QEMM v7.04 memory manager CR4use, eV86, enabled WRMSR TASM 3.2 Borland Pascal 7.0 Professional debugging TP 7.0 Borland Pascal 7.0 Professional making 'DB 66h' 32bit code CPUIDF.EXE Intel's Processor Detection Code CPUID, bug-free iPentiums CPU_ID.ZIP NexGen's Processor Detection Pack NexGen detection code sample ------------------------------------------------------------------------------ Thanks to c't magazine author Peter Siering for my 1st article in 11/94. Thanks to c't magazine author Andreas Stiller for testing all CPUID 'models'. Thanks to c't magazine author Georg Schnurer for testing and his knowledge. Thanks to Thomas Mönkemeier and his VGA-COPY/386 with my knowledge added in. Thanks to Harald Feldmann from the Netherlands for knowledge/letters/faxes. Thanks to Terje Mathisen from Norway for knowledge and his iPentium article. Thanks to Ralf Brown for adding some knowledge to his DOS-INT-database. Thanks to Peter Frühauf, the CBF-iPentium-60 and all the software-ß-testers. Thanks to Maciej Rozycki from Gdansk (Poland) for his excellent CPU knowledge. Thanks to Don Donato from Folsom (CA, USA) for the P24T test results (CPUID). Thanks to Michael Steele from the NexGen corporation for his CPUID support. Thanks to Alexander Konosevich for the Cyrix processor types and ID values. Thanks to Alex Wolfe for his articles about the 4P package in the EE Times. Thanks to Ingo Warnke for his basic knowledge for the V86 mode by-passing. ------------------------------------------------------------------------------ Peter Siering - ps@ct.ix.de - c't magazine (software) Andreas Stiller - as@ct.ix.de - c't magazine (processors) Georg Schnurer - gs@ct.ix.de - c't magazine (hardware) Michael Steele - michael.steele@nexgen.com - NexGen prod.market.manag. Harald Feldmann - feldmann@xs4all.nl (new!) - processor programming Mike Schmit - 76347.3661@compuserve.com - processor programming Terje Mathisen - terjem@hda.hydro.com - processor programming Maciej Rozycki - csa085mr@smokie.elka.pg.gda.pl - processor programming Thomas Mönkemeier - thm@vgasoft.com - VGA-Copy/386 and mailbox Ralf Brown - ralf@telerama.lm.com - DOS interrupt list Andrew Schulman - 76320.302@compuserve.com - book The undocumented DOS Frank van Gilluwe - 74000.635@compuserve.com - book The undocumented PC ------------------------------------------------------------------------------ Trademarks are the property of their respective owners. The file may be copied and distributed freely as long as it is distributed in its entirety and it is not distributed for profit. I don't guarantee anything. End of file! ------------------------------------------------------------------------------