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encoder.pal
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1991-01-12
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4KB
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79 lines
PAL20R4 PAL DESIGN SPECIFICATION
P7090 COLI/VOLPIGNO 10/13/82
15-INPUT REGISTERED PRIORITY ENCODER
MMI SUNNYVALE,CALIFORNIA
CLK I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND
/OC I10 I11 FLAG Q3 Q2 Q1 Q0 I12 I13 I14 VCC
; equations go here
/Q0 := /I0* I1
+ /I0*/I1*/I2* I3
+ /I0*/I1*/I2*/I3*/I4* I5
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8* I9
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12* I13
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13*/I14
/Q1 := /I0*/I1* I2
+ /I0*/I1*/I2* I3
+ /I0*/I1*/I2*/I3*/I4*/I5* I6
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9* I10
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13* I14
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13*/I14
/Q2 := /I0*/I1*/I2*/I3* I4
+ /I0*/I1*/I2*/I3*/I4* I5
+ /I0*/I1*/I2*/I3*/I4*/I5* I6
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11* I12
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12* I13
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13* I14
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13*/I14
/Q3 := /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7* I8
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8* I9
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9* I10
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11* I12
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12* I13
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13* I14
+ /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13*/I14
/FLAG = /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12*/I13*/I14
FUNCTION TABLE
CLK /OC I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q3 Q2 Q1 Q0 FLAG
; CHIP FIFTEEN INPUTS --OUTPUTS--
;CONTROL 11111 QQQQ
;CLK /OC 432109876543210 3210 FLAG COMMENTS
------------------------------------------------------------------------
C L XXXXXXXXXXXXXXH HHHH H I0 INTERRUPT HIGHEST PRIORITY
C L XXXXXXXXXXXXXHL HHHL H I1 INTERRUPT
C L XXXXXXXXXXXXHLL HHLH H I2 INTERRUPT
C L XXXXXXXXXXXHLLL HHLL H I3 INTERRUPT
C L XXXXXXXXXXHLLLL HLHH H I4 INTERRUPT
C L XXXXXXXXXHLLLLL HLHL H I5 INTERRUPT
C L XXXXXXXXHLLLLLL HLLH H I6 INTERRUPT
C L XXXXXXXHLLLLLLL HLLL H I7 INTERRUPT
C L XXXXXXHLLLLLLLL LHHH H I8 INTERRUPT
C L XXXXXHLLLLLLLLL LHHL H I9 INTERRUPT
C L XXXXHLLLLLLLLLL LHLH H I10 INTERRUPT
C L XXXHLLLLLLLLLLL LHLL H I11 INTERRUPT
C L XXHLLLLLLLLLLLL LLHH H I12 INTERRUPT
C L XHLLLLLLLLLLLLL LLHL H I13 INTERRUPT
C L HLLLLLLLLLLLLLL LLLH H I14 INTERRUPT LOWEST PRIORITY
C L LLLLLLLLLLLLLLL LLLL L NO INTERRUPT
X H XXXXXXXXXXXXXXX ZZZZ X TEST HI-Z
------------------------------------------------------------------------
DESCRIPTION
The 15-input registered priority encoder accepts 15 active low inputs
(I0-I14) to load the binary weighted code of the priority order into
the output registers (Q3-Q0) on the rising edge of the clock (CLK).