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Text File  |  1998-01-02  |  5KB  |  126 lines
  1. %! Detailed register description file for PCICFG.EXE by Ralf Brown
  2. %!
  3. %! Filename 80867100.PCI = Vendor 8086h, Device 7100h
  4. %!    Intel 82439TX System Controller
  5. %! Last Edit 31 Dec 97 by Andy Sawyer
  6. %!
  7. %! Reference : Intel document 29055901.PDF
  8. %! "Intel 430TX PCISET : 82439TX System Controller (MTXC)"
  9. %!
  10.  
  11. !begin
  12. 82439TX System Controller registers in detail:               [by Andy Sawyer]
  13.  
  14.  Extended CPU-to-PIIX4 PHLDA# Signalling: %[4F:7]ed
  15.  PCI Concurrency Enable:                  %[50:3]ed
  16.  ACPI Control Register:                   %[79:6]ed
  17.  Suspend Refresh Type :                   %[79:5]|CBR Refresh;Self Refresh|
  18.  Normal Refresh Enable:                   %[79:4]y
  19.  Internal Clock Control:                  %[79:2]ed
  20.  
  21.  Cache Control:
  22.    Seconday Cache Size:           %[52:7-6]|Not Populated;256K;512K;Reserved|
  23.    L2 SRAM Type:                  %[52:5-4]|Pipelined Burst SRAM;Reserved;Reserved;Two banks of pipelined burst SRAM|
  24.    NA Disable:                    NA is %[52:3]Ed
  25.    Secondary Cache Force Miss:    %[52:1]y
  26.    First Level Cache Enable:      %[52:0]ed
  27.    DRAM Cache L2 present:         %[53:5]y
  28.    DRAM Cache L2 refresh timer:   %[53:4-0]d
  29.  
  30.  SDRAM Control:
  31.    Special SDRAM mode select:     %[54:8-6](SDMS)
  32.    RAS# to CAS# Override:         %[54:5]ed
  33.    CAS# Latency:                  %[54:4]{23}
  34.    RAS# Timing:                   %[54:3]|3/5/8;3/4/7|
  35.    64-MBit Technology Enable:     %[54:1]y
  36.  
  37.  DRAM Control:
  38.    Refresh RAS# Assertion:        %[56:6]{45} Clocks
  39.    Fast EDO Lead Off:             %[56:5]ed
  40.    Speculative Lead Off:          %[56:4]Ed
  41.    Memory Address Drive Strength: %[56:2]|10;16|ma %[56:1]|10;16|ma
  42.    Memory Hole:                   %[57:7-6]|none;512K-640K;15M-16M;14M-16M|
  43.    Enhanced Paging:               %[57:4]ed
  44.    Detect Mode:                   %[57:3]ed
  45.    Refresh Rate:                  %[57:2-0]|disabled;15.6;31.2;64.4;125;256;Reserved|
  46.  
  47.  DRAM Timing:
  48.    Read Burst Timing:             %[58:6-5]|x444/x444;x333/x444;x222/x333;Reserved|
  49.    Write Burst Timing:            %[58:4-3]|x444;x333;x222;Reserved|
  50.    Leadoff Timing:                Read  %[58:0]|11;10|  Write %[58:0]{76}
  51.                                   RAS# Precharge %[58:1]{34}
  52.                                   RAS-to-CAS Delay %[58:0]{43}
  53.  
  54.   DRAM Boundaries:     %[60]3dM %[61]3dM %[62]3dM
  55.                        %[63]3dM %[64]3dM %[65]3dM
  56.   DRAM Row Type:
  57.      Host Frequency:   %[67:7]|60;66|MHz
  58.      DRAM Row Type:    Row 0: %[68:4]b%[68:0]b Row 3: %[68:7]b%[68:3]b
  59.      00=SPM 01=EDO     Row 1: %[68:5]b%[68:1]b Row 4: %[67:4]b%[67:0]b
  60.      10=SDRAM          Row 2: %[68:6]b%[68:2]b Row 5: %[67:5]b%[67:1]b
  61.      11=Reserved       
  62.      Memory Address Select Enable: %[67:2]d
  63.  
  64.  
  65. %! Note: Intel don't document leadoff timing as the above in as many words,
  66. %! but the answers are still the same :-)
  67.  
  68.  Programmable Attribute Map
  69.       0F000-0FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}\t0C000-0C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}
  70.       0C400-0C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\t0C800-0CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}
  71.       0CC00-0CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\t0D000-0D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}
  72.       0D400-0D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\t0D800-0DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}
  73.       0DC00-0DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\t0E000-0E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}
  74.       0E400-0E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}\t0E800-0EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R}
  75.       0EC00-0EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}
  76.  
  77.   Multi-Transaction Timer:           %[70:7-2]d
  78.   System Management RAM Control:
  79.      SMM Space Open:                 %[73:6]y
  80.      SMM Space Closed:               %[73:5]y
  81.      SMM Space Locked:               %[73:4]y
  82.      Global SMRAM Enble:             %[73:3]y
  83.      Compatible SMM Space base Seg:  %[73:2-0](C_BASE_SEG)
  84.      High SMRAM Enable:              %[71:7]e
  85.      Extended SMRAM Error:           %[71:6]y
  86.      SMRAM Cache Strategy:           %[71:5]|WriteBack;WriteThru|
  87.      SMRAM L1 Cache Enable:          %[71:4]e
  88.      SMRAM L2 Cache Enable:          %[71:3]e
  89.      TSEG Size:                      %[72:2-1](TSEG_SZ)
  90.      TSEG Enable:                    %[72:0]y
  91.  
  92.  
  93. !end
  94.  
  95. !enum SDMS
  96. Normal SDRAM mode
  97. NOP Command Enable
  98. All Banks Precharge Command Enable
  99. Mode Register Command Enable
  100. CBR Cycle Enable
  101. Reserved
  102. Reserved
  103. Reserved
  104. Reserved
  105. !end
  106.  
  107. !enum TSEG_SZ
  108. (TOM-128k) to TOM
  109. (TOM-256k) to TOM
  110. (TOM-512k) to TOM
  111. (TOM-1MB) to TOM
  112. !end
  113.  
  114. !enum C_BASE_SEG
  115. Reserved
  116. Reserved
  117. A0000-BFFFFh
  118. Reserved
  119. Reserved
  120. Reserved
  121. Reserved
  122. Reserved
  123. !end
  124. %! end of file
  125.  
  126.