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VHDL.TX
Wrap
Text File
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1997-02-25
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1KB
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176 lines
abs
access
active
after
alias
all
and
architecture
array
cending
assert
tribute
base
begin
block
body
buffer
bus
case
mponent
configuration
constant
delayed
disconnect
downto
driving
driving_value
else
elsif
end
entity
event
exit
file
for
function
generate
generic
group
guarded
high
if
image
impure
in
inertial
inout
instance_name
is
label
last_active
last_event
last_value
left
leftof
length
library
linkage
literal
loop
low
map
mod
nand
new
next
nor
not
null
of
on
open
or
others
out
package
th_name
port
pos
stponed
pred
ocedure
process
pure
quiet
range
record
register
reject
rem
report
return
reverse_range
right
rightof
rol
ror
select
severity
shared
signal
simple_name
sla
sll
sra
srl
stable
subtype
then
to
transaction
ansport
type
unaffected
units
until
use
val
value
variable
wait
when
while
with
xnor
xor
group
impure
inertial
literal
postponed
pure
reject
rol
ror
shared
sla
sll
sra
srl
unaffected
'active
'ascending
'base
'delayed
'driving
'driving_value
'event
'high
'image
'instance_name
'last_active
'last_event
'last_value
'left
'low
'leftof
'length
'path_name
'pred
'pos
'quiet
'range
'reverse_range
'right
'rightof
'simple_name
'stable
'succ
'transaction
'val
'value