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Text File  |  1993-06-14  |  3KB  |  120 lines
  1. ;
  2. ; SEEQ 8005
  3. ;
  4.  
  5. ; Registers
  6.  
  7. CMD    equ    00h            ;command (write only)
  8. STAT    equ    00h            ;status (read only)
  9. CONFIG1    equ    02h            ;configure 1
  10. CONFIG2    equ    04h            ;configure 2
  11. RXAREA    equ    06h            ;receive end area
  12. ;K2WR    equ    07h            ;ksetup 2 write
  13. ;KSTAT    equ    07h            ;kombo status
  14. BWIND    equ    08h            ;buffer window
  15. RXPTR    equ    0ah            ;receive pointer
  16. TXPTR    equ    0ch            ;transmit pointer
  17. DMAADR    equ    0eh            ;dma address
  18.  
  19. ; Command Register (CMD, write only)
  20. ;
  21. ENABLE_RX_INT    equ     0002h
  22. ENABLE_TX_INT    equ     0004h
  23. ENABLE_BUF_INT    equ     0008h
  24. ACK_RX_INT    equ     0020h
  25. ACK_TX_INT    equ     0040h
  26. ACK_BUF_INT    equ     0080h
  27. ACK_INT        equ     00ffh
  28. RX_ON        equ     0200h
  29. TX_ON        equ     0400h
  30. RX_OFF        equ     1000h
  31. TX_OFF        equ     2000h
  32. FIFO_READ    equ     4000h
  33. FIFO_WRITE    equ     8000h
  34.  
  35. ; Status Register (STAT, read only)
  36. ;
  37. RX_INT        equ     0020h
  38. TX_INT        equ     0040h
  39. BUF_INT        equ     0080h
  40. ALL_INT        equ     RX_INT
  41. FIFO_FULL    equ     2000h
  42. FIFO_EMPTY    equ     4000h
  43. FIFO_DIR    equ     8000h
  44.  
  45. ; Configuration Register 1 (CONFIG1)
  46. ;
  47. BUFFER_BITS     EQU    000fh
  48. ID_REG_0    equ     0000h
  49. ID_REG_1    equ     0001h
  50. ID_REG_2    equ     0002h
  51. ID_REG_3    equ     0003h
  52. ID_REG_4    equ     0004h
  53. ID_REG_5    equ     0005h
  54. ADDR_PROM    equ     0006h
  55. TEA_REG        equ     0007h
  56. BUFFER_MEMORY    equ     0008h
  57. INT_VECTOR    equ    0009h
  58. ;
  59. ID_0_ENABLE    equ     0100h
  60. ID_1_ENABLE    equ     0200h
  61. ID_2_ENABLE    equ     0400h
  62. ID_3_ENABLE    equ     0800h
  63. ID_4_ENABLE    equ     1000h
  64. ID_5_ENABLE    equ     2000h
  65. MATCH_ID    equ     0000h+0000h
  66. MATCH_BRDCAST    equ     0000h+4000h
  67. MATCH_MULTICAST    equ     8000h+0000h
  68. MATCH_ALL    equ     8000h+4000h
  69.  
  70.  
  71. ; Configuration Register 2 (CONFIG2)
  72. ;
  73. REA_UPDATE_ON        equ     0002h
  74. LOOP_BACK        equ     0800h
  75. WATCH_TIME_DIS        equ    1000h
  76. RESET_BIT        equ     8000h
  77. SHORT_FRAME_ENABLE    equ     0020h
  78. DRIBBLE_ERROR_ENABLE    equ     0010h
  79. CRC_ERROR_ENABLE    equ     0008h
  80. DISABLE_LOOP_BACK_RX    equ     1000h
  81.  
  82. ;
  83. ; Transmit Header
  84. ;
  85. TX_DONE        equ     80h
  86. COLL16        equ     04h
  87.  
  88. TX_COMMAND    equ     0ach
  89. ;Transmit (80h), Data follows (20h), Xmit succ enable (08h), 16 coll (04h).
  90.  
  91. ;
  92. ; Receive Header
  93. ;
  94. ; Description of header of each packet in receive area of memory
  95.  
  96. RBUF_SIZE_HI    equ    0    ; Length of this frame
  97. RBUF_SIZE_LO    equ    1    ; Length of this frame
  98. RBUF_HDR    equ    2    ; Header information
  99. RBUF_STAT    equ    3    ; Received frame status
  100. RBUF_NXT_PG    equ    1    ; Page after this frame
  101. RBUF_NHDR    equ    4    ; Length of above header area
  102.  
  103. RX_CHAIN    equ    40h
  104. RX_DONE        equ     80h
  105. RX_ERROR    equ     0bh
  106.  
  107. ; Misc.
  108. ;
  109. TX_BUF_CNT    equ     4
  110. BUF_SIZE    equ     0600h
  111.  
  112. TX_AREA_BEG    equ     00000h
  113. TX_AREA_END    equ     (TX_BUF_CNT * BUF_SIZE) - 1
  114. RX_AREA_BEG    equ     TX_AREA_END + 1
  115. RX_AREA_END    equ     0FFFFh
  116. RX_AREA_SIZE    equ     RX_AREA_END - TX_AREA_END
  117.  
  118. FIFO_Count    equ    6000
  119.  
  120.