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CLA LOGIC v2 ============ Beta Test Release 4 NOTE: This document is a conversion & update of the CLA v1 (unregistered) manual - done in about an hour and a half. This means that it isn't very good...it is intended as a stop-gap measure until either a new manual is written, or an on-line help facility is added. =========================================================== CLA Version 2 Release 1 (Beta4) USER MANUAL (Summary) =========================================================== Copyright 1993, By Data Uncertain Software. Written By Craig Graham. =========================================================== CONTENTS -------- 1. INTRODUCTION 2. INSTALLATION 2.1 Unpacking 2.2 Files 2.3 System Required 2.4 Loading 3. THE CLA ENVIROMENT 3.1 Pull-down Menus 3.2 The Status Window 3.3 Editor Windows 3.4 The Main Menu Bar 3.5 Tool Boxes 3.6 CLA Dialog Boxes 3.6.1 Pop-up menus 4. BASIC DESIGN PROCESS 4.1 Placing Components - The Basic Gates Toolbox 4.2 Linking Components 4.3 Adding Inputs 5. THE FILE MENU 5.1 Save 5.2 Load 5.3 Printing & Metafiles 6. SIMULATION 6.1 The Tools Icon 6.1.1 Bulbs 6.1.2 Logic Scope Probes 6.1.3 The Logic Scope 6.1.4 The Active Probe 6.2 Running A Simulation 6.2.1 Inputs during Simulation 6.2.2 The Active Probe & The Scope 6.3 Clocked Inputs 6.4 The Word Generator 7. OTHER FEATURES APPENDIX A : KEYBOARD SHORTCUTS APPENDIX B : LIBRARY MODULES 1.0 INTRODUCTION ================= This manual is intended as a 'get you going' sort of guide to the CLA Logic design & simulation package. Due to the highly iconic nature of the program, and the textual nature of this manual, it is not intended as an in-depth tutorial and referance. A complete manual is available to registered users (see README.DOC for details). CLA is intended as a tool to enable fast prototyping of digital circuits. The inspiration as to it's approach to this is rooted firmly in the UN*X world, where several high end packages costing several thousand pounds offer similar features (although much wider in scope of course, with a price tag of several thousand pounds, we could do this as well, but then we couldn't release as shareware). The design part of the package (perhaps a bad description, as design & simulation are completely integrated) supports the standard set of logic gates (ANSI style representations only for now I'm afraid - perhaps a set of IEEE symbols will be made available at a later date, or you could draw up your own with VECED2), and also a few librarys of standard components (eg, flip-flops, adders, etc) and IC's (the 74xx TTL series). A subset of VHDL is provided for textual circuit description. The integrated simulation section of the program can be accessed at any time and provides interactive use of the circuit, with Logic scope analysis, 'live' indicator bulbs, active logic probes, etc, or more formal testing from an integrated Word Generator. The whole enviroment is graphical, using icons, windows, 'flying' dialogs and the mouse to produce & simulate the design. Not wanting to labour a point, but CLA is SHAREWARE. If you find it at all help full then REGISTER - you can then make sugestions for extra features you need.....if you don't register then you get no support from the authors at all. 2.0 INSTALLATION ================= 2.1 UNPACKING -------------- The fact that you have reached this point in the documentation at all sugests that you have sucessfully unpacked the file 'CLA_V2R1.ZIP'. 2.2 FILES ---------- If you have used STZIP 2.x, then the correct directory structure should already be set up for you. Just as a check however: Once unpacked, you should have the following file & directory structure :- .\ CLA.PRG CLA Design & Simulation Enviroment VECED2.PRG Vector Object Editor LIBV1.PRG Librarian README Notes on this beta release, and a survey to return. INVENTOR.Y The file inventory (almost certainly more up to date than what you are reading now. .\DOC COPYRGHT.TXT How you can copy this. BUGLIST Known Bugs CHANGES.TXT New stuff from the last release. FUTURES.TXT Stuff currently under developement MANUAL.TXT This file. VECEDIT.TXT Quick notes on the Vector Object Editor VECED2. TOS4SCR1.GIF Screenshots (GIF format) of CLAv2 in it's full glory on TOS4SCR2.GIF a Falcon. FSM_EDIT.GIF .\EXAMPLES Several example .NET files to play with. .\FSM_DES FSM_EDIT.PRG The Finite State Machine design program. SDES.RSC Resource file for the above (colour only). B.FSM Example state machine files. V6.FSM README.TXT Doc's for the state machine editor. .\VHDL README The VHDL compiler documentation. CLA_VHDL.PRG VHDL subset to CLA.NET compiler. CLAVHDLC.RSC Resource file for the above (colour). CLAVHDLM.RSC Resource file for the above (mono). OPERATORS.CLA File giving operator precedence for the VHDL compiler. .\VHDL\74XX.VHD The VHDL source for the standard 74 series TTL library 7400.VHD 7402.VHD 7404.VHD .\RESOURCE.CLA BWLOGIC.NAM Various CLA resources CLAC.RSC CLAM.RSC FILE.GTB GATES.GTB INPUTS.GTB TOOLS.GTB LIBV1C.RSC Librarian resources (colour & mono) LIBV1M.RSC VECEDITC.RSC Vector Object editor resources (colour & mono) VECEDITM.RSC .\RESOURCE.CLA\VECTORS DEFAULT.VFN CLA vector font - primitive, but effective. GATES.VEC Standard logic gate images (editable with VECED2) .\CONFIG.CLA FANOUT.DEF The average fanouts available from various IC technologies KEYS.DEF Keyboard shortcuts definition file. LIB.DEF The library definition file (editable with LIBV1) .\LIBRARY The modules library for CLA. .\LIBRARY\74XX The 74 series TTL library (from VHDL sources) 7400.NET 7402.NET 7404.NET .\LIBRARY\USERLIB A predefined but empty library for your stuff. .\LIBRARY\BASIC Simple things such as 2-bit adders & D-flip-flops If anything is missing then you have problems. NOTE: CLA MUST have this directory structure, or it WILL NOT work. You can place the root of this structure ( .\ ) anywhere, but must keep all things in the correct directories after that. If you wish to use the printed output facility, then you will require GDOS, FontGDOS, SpeedoGDOS or NVDI (I use NVDI) to be installed as well. It is beyond the scope of this document to explain the complexities of installing GDOS (someone write & tell US about that black art !!!), so the only comment to make on that is that the program expects to find a device driver available as device 21. This is usually the EPSON FX80 driver and as this is the only printer we have available to us, it's the only on that is tested at the moment, but we ASSUME that other drivers will work as long as they are installed as device 21 in the ASSIGN.SYS file. GEM Metafile output is also available, and the above applies to that as well, but META.SYS must be installed as device 31. This program mayu not work with FSMGDOS - but, hey if you're using that then you deserve all you get anyway. 2.3 SYSTEM REQUIRED -------------------- The basic system required to run CLAv1 was :- - 512K ATARI ST - 1 Double sided disc drive - Monochrome monitor This is no longer the case (sorry...) The basic system required to run CLAv2 is :- - 2Meg ATARI ST - 1 Double sided disc drive - Monochrome monitor The above is not ideal however. The recomended system for running CLAv2 is :- Platform : MegaSTE / TT / Falcon Memory : 4Meg - required for running CLA at higher res. Storage : Hard drive, requires 1 Meg for basic installation - this WILL increase quite drasticly as the synthesis tool & FSM designer are added. Display : Crazy Dots / TT / Falcon extended (FalconScreen/Blowup030) + a gfx accellerator (Warp9 / NVDI), in min. 16 Colours. OS : TOS 4.02, multiTOS 1.04+. Our developement system is :- Platform : Falcon Memory : 4Meg Storage : 85Meg Hard drive Display : 800x600x16colour Falcon extended (FalconScreen) + NVDI2.5 OS : TOS 4.02 + WINX2.1 (highly recomended - it's great). This is quite a large jump in system requirments, but hey, the jump from v1 to v2 has been really quite severe. 2.4 LOADING ------------ To load CLA, click on 'CLA.PRG'. The program should then load and run. Alternatively, CLA may be installed using the INSTALL APPLICATION option from the desktop, using a '.NET' file extension. This allows the program to be run by double clicking on a .NET file (these are the circuit designs). In TOS 3/4/MultiTOS, CLA.PRG should be installed to default to it's OWN directory, not the top window's, and should be passed the whole path to a file. While CLA loads, a window is displayed indicating what CLA thinks your system is. If you have a problem, not down the info from here - it'll help me to sort you out. Click the left mouse button to get past this start-up window. It will close, and the main program window will open. 3.0 THE CLA ENVIROMENT ======================== 3.1 Pull Down Menus -------------------- Most CLA options are available from both the standard GEM pulldown menus at the top of the screen or from the various Toolbox windows which can be opened. There are also keyboard shortcuts for most frequently used things. CLA starts up with 3 windows displayed. 3.2 The Status Window ---------------------- At the top of the screen is a status window which reports actions (such as PLACE GATE, MOVE GATE, etc). This window is fixed - you cann't move it, you cann't close it. It can be overlayed by other windows, and can be topped by clicking in it, but thats all. 3.3 Editor Windows ------------------- Filling most of the screen is an empty window. This is a schematic window in which you will do your designing. Re-sizing, moving & scrolling of this type of window are as you would expect in a GEM application, however, the full & close widgets are used slightly differently. Close behaves like the MS Windows / OSF Motif top left button, and drops down a menu, of which close is only one of several options (eg. ICONIFY will turn a window into an icon, SISTER WINDOW will produce another window with the same contents as the first). The Full widget pops up another menu, this time one with several Icons and buttons in it. From left to right, these are: - Windowed mode display. Sets this window to display graphics at a set scale and force you to scroll around the design using the scroll bars. The actual scale is set in the configuration dialog. - Scaled mode display. Sets this window to display the whole design in the window, rescaling it to fit as you resize the window. The scroll bars are ignored here. - '⇩' = Iconify. This does the same as selecting Iconify from the Close Pull-down. - '⇧' = Full. This does what the full widget would normally do in most GEM programs and sets the window to full screen. 3.4 The Main Menu Toolbox -------------------------- The Main Menu Toolbox is displayed on the right hand side of the screen at start-up. It may be move freely (it's in a GEM window), but in ST High there is very little room to move it into. Unlike all other Toolboxes in CLA, the main menu cannot be closed or Rolled up - it is there all the time. It's icons (in top down order) have the following functions:- - REFRESH Forces the current schematic window to redraw. - LINK Selects the link-up mode for joining up components. - CUT LINK Selects the disconnect components mode. - DELETE ITEM Enters Delete mode for deleting gates, inputs & blocks. - ROTATE As it's name sugests, this icon put's you into rotate mode. Now, clicking on any gates will cause them to rotate by 90°. - GATE The five bar gate icon opens the GATES Toolbox. The Gate Toolbox allows you to chose which type of basic gate to place (AND, OR, NOT, etc). - INPUTS This opens the INPUTS Toolbox, where inputs (both manual & clocked) and outputs (hierachical) are set. - MOVE This icon selects MOVE GATE MODE. This allows you to click on and move gates which you have put in the wrong place. - BLOCK Selects block create/enter mode for hierachy manipulation. - FILE Opens the FILE Toolbox for the usual save/load/exit/library functions. 3.5 Toolboxes -------------- In general, a toolbox window in CLA is open which just contains icons for various functions (some of which cannot be accessed from anywhere else). All other Toolbox windows in CLA (apart from the Main Menu) are 'Roll-ups' - ie. clicking on the Full Widget (top right of the window) when they are open will cause the window to 'Roll up' leaving just the top bar (this stops things getting to cluttered). They are restored by selecting the Full Wigdet again. The close button simply closes the window. If you have TOS 3/4/MultiTOS then icons in toolbar windows can be accessed in the background without topping them. WINX also supports this. 3.6 Dialog Windows ------------------- Note that ALL CLA dialogs appear in windows. This means that you can move them and work in editors without actualy closing a dialog. 3.6.1 Popups ------------- Inside CLA dialogs, there may be changable fields (eg, the font in the printout dialog). Clicking on these will popup a menu for you to select from. The downside of having everything in windows, is that older TOS versions will start to run out of windows (the program then starts behaving a bit strangely) - so you are best to install WINX if you have an older TOS (<2). 4.0 BASIC DESIGN PROCESSES =========================== This section details how to produce SIMPLE designs. More complex designs require much more though, and a substantial use of the BLOCK structuring facility is really necassary. 4.1 PLACING COMPONENTS ----------------------- To produce a design, you must first place some components. In order to do this you must select the GATES icon and then select a type of gate to place from the Gates Toolbox which then appears. Alternatively select a gate type from the gates pull-down menu. Now whenever you move the cursor within the schematic window, you can place a gate at the current location by pressing the left mouse button. If you hold down the button, then move the mouse, you can make the gate you are placing face left, right, up or down. Whilst in the schematic window, the mouse pointer will be replaced by a set of cross hairs. The schematic window does not have to be on top in order to edit thing in it. You can place a gates toolbox window in front of the schematic for quick gate selection, then place things straight into the schematic WITHOUT topping the window. 4.2 LINKING COMPONENTS ----------------------- Once you have a few components on the screen, you will want to connect them together. To do this you use the LINK icon. Once selected, this icon places you in link mode. To create a link between two components, you then only have to click on the source gate, and then point at the destination gate. If there is a spare input to the destination gate, then a line will be drawn between the two. To select the desination gate, press the LEFT mouse button. NOTE: Pressing the RIGHT HAND BUTTON will cancel a link. Once source & destination components are selected, you must draw a wire path between the two. This is for your referance, and drawing a silly wire path will NOT effect the simulation at all. An 'L' cursor is used whilst drawing the wire path. To add a point to the path, press the LEFT BUTTON. Pressing the right hand button will terminate the wire. Also, with single input gates, if you happen to add a point to the wire which coincides with the input terminal of the gate, then the wire will terminate itself. Pressing ALTERNATE whilst drawing a wire path will swap the orientation of the link path: ---------+ + | | | | | | | | | | | | + +---------- 4.3 ADDING INPUTS ------------------ A circuit is not much use with no inputs, so inputs may be added using the ADD INPUTS icon. This can be found in the INPUTS menu which is invoked by selecting the INPUT icon on the main menu. The icons on the INPUTS menu are as follows (left to right): - ADD INPUT : Adds a manually togglable input to the circuit. If within a block, this adds an input connector from the next level up from that block to this level. ----------- | | | | | | -->input | | | | | ----------- - ADD OUTPUT : This adds am output connector from a block to the next Level up in the design. If you are NOT within a block then this icon does nothing. - ADD CLOCK : This adds an auto-clocked input to the circuit. (See section 6.3) NOTE: All hierachical input / output connections are dealt with in the REGISTERED USER documentation. This is not to say that the block structuring features are at all disabled in this release, only that their usage is not documented here. Pay or play - I'd prefer you to pay. When ADD INPUT is selected you will be asked to place the input. As a matter of readability, the program will automatically place ALL external inputs at the left of the screen. Only the vertical position of the input can be altered. The input connector will now appear and you should now point to the gate to which the input should be connected and click the LEFT BUTTON. As with linking gates, pressing the RIGHT BUTTON will cancel the input. Once an input destination is selected, you should then draw a wire path in exactly the same way as when linking gates togther. NOTES: ------ (1) EACH INPUT CAN GO TO ONLY ONE PLACE. TO FEED AN INPUT TO MORE THAN ONE PLACE, FIRST CONNECT IT TO A DRIVER GATE (NOP), THEN CONNECT THE DRIVER TO EVERYWHERE ELSE. 5. THE FILE MENU ================= The FILE menu is opened by the FILE icon at the bottom of the main menu. The icons in the FILE menu are (from left to right): - LOAD : Load a circuit design from disc. - SAVE : Save the present circuit design to disc. - LIBRARY : Insert a module from the libraries into the present block. - PRINT : Open the GDOS output Dialog Window. (Only useful if GDOS is installed.) - USER : Open the configuration window where the following options can be set: i) Grid snap (ON/OFF) ii) X-Y coordinate readout (ON/OFF) iii) Auto part name (ON/OFF) iv) Scope Resolution. This is actually a misnomer. The value of Scope resolution is really the number of gates through which a signal will propogate for each basic clock cycle / Logic Analyser update. v) Drawing scale - EXIT : This either exits the present drawing and leaves a blank workspace, or quits the program. 5.1 SAVING ----------- Select SAVE from the FILE menu. Follow the usual GEM procedure for selecting a file, then do as the alert boxes say. Overwriting of existing files is trapped, but out off disc space errors will kill the program (sorry). 5.2 LOADING ------------ As above, but use the LOAD icon instead. Only one design may be loaded at once. The multiple schematic windows (sister windows) are intended to allow editting of several hierachical blocks at once within the same design. 5.3 PRINTING & METAFILES ------------------------- Nice and easy - to procedure for printing is as follows:- 1) Go to the block you wish to print. 2) Select the PRINTOUT option from file menu The 'Hardcopy Output' dialog will appear. 3) Set what you want to print - the circuit diagram or the contents of the Logic Analyser window. 4) Set the font type you wish to use. GDOS fonts look better, but CLA-VECTOR fonts are useful for programs such as Pagestream & Calamus 1.09, which have problems with normal GDOS fonts - they're just drawn as line vectors, so Calamus will load & display them properly. 5) Select the output destination - either hardcopy (device 21) or metafile (device 31). 6) Click on PRINT. The progress window will now appear, and give a report on how printing is progressing. NOTE : For best results when printing circuit diagrams, set the PAGESIZE so that the circuit will fill the page, otherwise you will not be able to read the text labels on a low res. printer (<300dpi). 6. SIMULATION ============== The main features of CLA are the simulation modes. These can be invoked at any point in the design process. The only prerequisite is that at least one input to the circuit should be connected up (otherwise no stimulus can be given to the circuit). 6.1 THE SIMULATION TOOLS ICON ------------------------------ Before simulating a design, it is neccesary to become familiar with the facilities available via the SIMULATION TOOLS toolbox, or the Simulation pull-down menu. - LOGIC ANALYSER This is a large looking double icon, which if clicked on will open the Logic Analyser window. - SET PROBE Allows you to specify which signals will appeat in the logic analyser. - PRINT LOGIC ANALYSER. Prints out the present state of the Logic Analyser Display. (Only works with GDOS installed). - ACTIVE PROBE. Toggle the active probe (ON/OFF) - WORD GENERATOR. Allows a preset series of signals to be fed to the design. - BULB. Select place bulb. 6.1.1 BULBS ------------ The bulb icon is really a just a component the same as all the gates in the Gates Selector. Once selected, you can (if you close the TOOLS window) place bulbs in the same way as ordinary gates. The differance between a bulb and a gate is that the bulb will show graphically on the screen the state of it's input (high or low). If the input to a bulb is high then the bulb will be black, where-as if the input is low then it will be white. ********NOTE: BULBS ARE CURRENTLY DISABLED IN CLA V2 DUE TO A SHORTAGE ******** OF DEVELOPMENT TIME (I BROKE THEM AT THE LAST MINUTE). ******** ONLY USE THE LOGIC ANALYSER WINDOW FOR NOW. 6.1.2 LOGIC ANALYSER PROBES ---------------------------- Bulbs are only updated and displayed if they are currently visible, so they cannot be used to compare signals in differant blocks of the design. More useful for any complex analysis is the LOGIC ANALYSER. This allows probes to be set on the output of any component in the circuit, and this will produce a trace in the logic analyser window (see section 6.1.3). To set a Logic Analyser probe, you click on the right hand side of the Logic Analyser Icon (the big one at the left hand side of the TOOL window). This selects the SET PROBE function. You will be prompted to select a component to set the probe on. Click on the component, and you will be prompted for a Scope Trace. This can be any number from 1 to 20 (there are 20 traces available you see, and you have to use one of them). A probe is now set, and the appropriate trace will be updated when a simulation is run. 6.1.3 THE LOGIC ANALYSER ------------------------- This is the main tool in simulating designs. It allows the response of selected components to be monitored and compared in pseudo-realtime. There are 20 traces visible simultaneously. The assignment of these probes is detailed in the previous section. Selecting the Logic Analyser Icon (the big icon in the TOOLS window) opens the Logic Analyser window. There will only be actual traces displayed for the traces which have been assigned using SET PROBE. In order to see the results of a simulation, the Logic Analyser window should be OPEN during simulation (otherwise you cann't see the traces). 6.1.4 THE ACTIVE PROBE ----------------------- This function when enabled, allows the output of any gate to be checked DURING interactive simulation, without having first set a probe of any type on it, and without stopping the simulation. To use the Active Probe, simply select it's icon, then start a simulation. To check a gates status, simply point and click with the LEFT HAND MOUSE BUTTON. The active probe may be used in conjunction with any of the other simulation tools available. 6.2 RUNNING A SIMULATION ------------------------- To actually start a simulation running you use the RUN SIMULATION icon from the main menu. This can be done at any time during the design process, PROVIDED THAT YOU HAVE GIVEN THE DESIGN AT LEAST ONE EXTERNAL INPUT. When simulating, the message 'RUNNING SIMULATION' appears in the status window. A simulation is stopped by pressing the RIGHT HAND MOUSE BUTTON. If the scope window is open then it will be updated whilst the simulation is running, and will scroll to show results. Any bulbs currently on screen will be updated. NOTE: Any un-connected inputs to gates will be tied LOW. 6.2.1 INPUTS DURING SIMULATION ------------------------------- In order to do useful simulations, you must be able to modify the inputs to simulate the expected inputs to the system and examine it's response. To do this, the status of any input can be toggled between it's high and low states by pointing at the required input in the TOP LEVEL of the design and pressing the LEFT HAND MOUSE BUTTON. A dot is displayed in the middle of the input connector to show it's status. This should be done whilst the simulation is running, and allows the design to be used interactively. 6.2.2 THE ACTIVE PROBE & THE LOGIC ANALYSER DURING SIMULATION -------------------------------------------------------------- The Logic Analyser is updated during simulation to reflect the state of the circuit as it is affected by the inputs. NOTE : The ACTIVE PROBE does not interfere with this. In the case of the active probe being turned on during simulation, the input toggle will have priority over the active probe at the left hand side of the screen. 6.3 CLOCKED INPUTS ------------------- Digital systems will quite often be required to perform things in a specific sequence or at a certain time. In these circumstances (such as computer systems design) the system is driven by a clock signal. In order to simulate clock driven systems, you could sit and manually toggle the inputs (but you would get sore fingers). Instead, CLA provides a special type of input, which provide a clock signal at a specified rate. A clocked input is added using the ADD CLOCK icon from the INPUTS menu (see section 4.3). The input is placed and connected up in exactly the same way as for a normal input (except that you select ADD CLOCK instead of ADD INPUT). Once connected up however, you are prompted for a CLOCK FREQUENCY DIVIDER. This is an important concept, so you must understand this to use clocked inputs. It is possible for a system to have more than one clock signal, at differant frequencies. The frequency divider allows this to be simulated by relating the frequencies of all the clocks in the system to one SOURCE FREQUENCY. The SOURCE FREQUENCY is the frequency of the highest speed clock signal which is going to be used by the system. All other clocks are based on this frequency, divided by some whole number (the FREQUENCY DIVIDER). The SOURCE FREQUENCY clock would have a clock divider of 1. A clock of HALF the frequency would have a clock divider of 2. In general : SOURCE FREQUENCY ----------------- = CLOCK FREQUENCY FREQUENCY DIVIDER Confused ? Here is an example set of clock frequencies and dividers to let you see what I'm getting at : +-----------------+---------------+---------------------------------------+ | CLOCK FREQUENCY | CLOCK DIVIDER | REASON | +-----------------+---------------+---------------------------------------+ | | | | | 1 KHz | 1 | This is the highest clock frequency | | | | needed (the SOURCE FREQUENCY). | | | | | | 500 Hz | 2 | 1000 Hz / 2 = 500 Hz | | | | | | 10 Hz | 10 | 1000 Hz / 10 = 10 Hz | | | | | +-----------------+---------------+---------------------------------------+ If things still aren't clear, register and then you can ask me personally what this all meant. NOTE : Clocked inputs cannot be toggled manually. 6.4 THE WORD GENERATOR ----------------------- This is a window in which all inputs to the circuit are listed. It runs seperate from the interactive simulator, but shares the same logic analysers. A series of logic levels (1/0 currently) may be set up, and these will be used as input to the circuit when the GO button is selected. All the inputs will be fed to the circuit in turn, then the simulation will terminate & the logic analyser window will be updated to display how the circuit has behaved during the simulation. This is 'BATCH MODE' simulation, as once started there can be no interaction from the user. To put this in perspective, it should take not more than 20 seconds to do a very large circuit (1000's of gates) with a scope res of 512 gates delays per scope step. Most circuit's will appear to simulate instantly (using scope res around 64). 6.5 SCOPE RES. --------------- The scope res. is important, as it set's the maximum measurable/changable resolution of the simulator in terms of unit gate delays. So, a res. of 1 means that the signal will propogate through exactly one gate before the logic analyser updates again. This also means that you can change the signal after one unit delay. This can be good or bad depending upon circumstances. A problem is that you can generate clocks which are faster than the time required to latch data into a register. Eg, the D-FLIPFLOP in the User_lib library requires a clock of period > 32 gate delays. If you use a higher scope res (ie lower number of unit gate delays), it's quite possible for the design to stop working (just like using too fast a clock in the real world). A good rule of thumb is to set the scope res to 32 in most cases. 7. OTHER FEATURES ================== This document was merely intended to get people stared using CLA. It does not cover the more advanced features such as : - BLOCK structuring & hierachical design. (Hint - in block mode, LEFT button is for pushing down into blocks, RIGHT button is for creating new blocks. Go back up using the close button pop-up menu option 'Go-back'.) - Loading Library modules. - The Librarian program and creating user libraries. - Creating Custom schematic gates sets. - Using the VHDL compiler. These features ARE in the V2 RELEASE 1 package, but are not detailled in this document. Their use is a matter of trail and error on the part of unregistered users. Registered users will, however recieve FULL documentation of these features (of course YOU are an honest person aren't you ? I'm sure you wouldn't use an unregistered SHAREWARE program - would you....) There is a lot more pencilled in for the next release of CLA. Registered users will recieve this as a matter of course, but it is open to debate as to whether the next release will be made available via FTP & the nets. Certainly, the Synthesis tool extensions will NOT be made generally available (when I've finished them) apart from to registered users. APPENDIX A : KEYBOARD SHORTCUTS ================================ Most functions of CLA may be accessed via keyboard shortcuts as well as the icons. These keyboard shortcuts are accessed by merely pressing shift + the appropriate key, NOT via Control or Alternate. Note that currently they aren't very reliable, you'd be better using the actual icon or the pull-down menu option. The keyboard shortcuts presently defined may be found in the file: '\CONFIG.CLA\KEYS.DEF' Other icons may be assigned to the keyboard by adding their names to this file. The names can be found in the file: '\DOC\SHRTCUTS.TXT' **** NOTE: THIS FILE IS NOT INCLUDED WITH THIS RELEASE APPENDIX B : LIBRARY MODULES ============================= You may have noticed the LIBRARY icon on the FILE menu. This as it's name indicates, allows library modules to be loaded in (such as IC's) and used within your designs. Clicking on the LIBRARY icon brings up something similar to a file selector. This is the Library Module Selector. It gives the name of the current library (changable by clicking on name of the library at the top of the selector), followed by a list of the library's contents. Clicking on a module name, or it's description, will bring up an Alert Box to confirm that you want to include this module. If you confirm this then the module will load and there will be a short pause whilst the module is mapped into your design. A ghost outline of the module is then displayed and this may be moved around the screen using the mouse. Clicking a mouse button will cause the block to be placed at the current location. The module is now just like any other hierachichal block, and it's inputs and outputs can be connected up as normal. The library modules may even be opened up to examine the way we at Data Uncertain implemented the module, with the exception of VHDL blocks (those displayed with a big V in them) such as the 74xx library,as these do not contain meaningful schematics anyway. APPENDIX C : ABOUT THE THE AUTHOR ================================== DATA UNCERTAIN SOFTWARE is made up of: Craig Graham : Main GUI code, Compiler type simulation routine & main code, VHDL, Librarian, vector editor. (BAe SPACE SYSTEMS, Stevenage, England) EMAIL : Craig.Graham@newcastle.ac.uk Plain Mail: 46 School Road, Langold, Worksop, Notts, S81 9PY, ENGLAND And to varying degrees, the contributions of the following people: Peter Brooks-Johnson : Design section User interface & Fanout Checking, Look & feel of Editor GUI (design of). (Even though I've removed the Fanout stuff for now.) SPOUT Spice OUTput (if he ever finishes it). (British Telecom, England) EMAIL : P.A.Brooks-Johnson@newcastle.ac.uk Malek Jaber : Some programming, but I've forgotten what (sorry Mal). Forcing the structured rewrite upon me. (3 Comm, Hemlhampstead, England) Chris Forker , Julian Coleman & Sime Harrison : Beta testing on the MegaST, TT & STE respectively. Chris Cuckow : For his enthusiasm in the early years. Kev R. & Tom McC. : Just for being cool and making us go to the clubs and get off with girls and get drunk and.... well, relax and live a little. All authors are students currently studying for their Masters Degrees in Microelectornics And Software Engineering at Newcastle University, England, sponsored by and working for the companies quoted above during their vacations. CLA was intended mainly as a tool for helping the authors through their degrees. As there are 2 years left to go before graduation, there will be at least that many years of support & development for the program. The authors may be contacted via EMAIL or Plain Mail at the addresses given above. EMAIL is appreciated, espescially from non-registered users, as replies are easier and quicker to send (and don't cost us anything). In fact unregistered users are UNLIKELY to get replies to anything apart from EMAIL, unless they enclose some money.... Alternatively, I may be contacted via the USENET groups : comp.sys.atari.st comp.sys.atari.st.tech Which I read during term time. Enjoy the program....it's our pride and joy. CRAIG GRAHAM