Labels:text | diagram | plan | technical drawing | schematic | sketch OCR: U.S. Patent Main Loop - Translation Look Aside Buffer Most significant bits Most significant bits Control of virtual address of physical address bits A/N,T No In translation Yes buffer Jul. 20, 1999 generate Translate exception T Decode Convert to primatives access Optimize Compare physical pass address Compare foil Schedule for processor Sheet 5 of 7 Add to translation buffer Most significant Type of address bits of oddress Mem or 1/0 Translated instruction(s) Execute translation 5,926,832 Figure 7 Figure 11
