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1979-12-31
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225 lines
A Forth Z80 Assembler for F83 V2.1.0 14 Feb 1990
------------------------------------
by E. Smeda
1. Introduction
This program adds Z80 assembly facilities to the 8080 assembler
included with Laxen & Perry's F83 FORTH (version 2.1.0 for CP/M-80).
It allows the programmer to make use of the extra assembly language
instructions provided by the Zilog Z80 or compatible microprocessor.
Intel 8080 mnemonics are retained for those instructions common to
both the Z80 and the 8080 CPU. For the additional Z80 instructions,
a set of mnemonics popularized by Technical Design Labs has been
chosen (usually known as 'TDL' mnemonics).
2. Installation
To install the new assembler, place F83.COM and F83-ZASM.BLK on
the same disk. From the CP/M prompt, type -
A> F83 F83-ZASM.BLK <cr>
8080 Forth 83 Model
Version 2.1.0 Modified 01Jun84
1 LOAD <cr>
loading Z80 assembler additions ok
The new Z80 instructions are now included in the assembler. Should
you wish to include the assembler additions permanently with F83,
type -
SAVE-SYSTEM F83NEW.COM <cr>
3. Usage
Using the new assembler is no different from using the 8080 version.
As with the original, it is still possible to assemble nonsense code
without an error warning so care should be execised.
4. Improvements
For those liking a challenge, an obvious improvement to the
assembler would be to modify the meta 8080 assembler in the F83
system source files. This would allow the user to rewrite F83's
kernel, replacing some of the inefficient 8080 code.
5. Forth Z80 Assembler Mnemonics
The following chart lists those instructions additional to the
Intel 8080 instruction set and which the Z80 processor may execute.
The first column shows the Zilog standard mnemonics followed, in
the second column, by the TDL mnemonics used for this assembler.
Note: As is usual in forth assemblers, the operands precede the
opcodes. Where an instruction requires two operands the order of
the operands must be as indicated.
b bit position (0-7)
d displacement added to IX or IY registers (0-255)
r register A,B,C,D,E,H or L
n 8 bit operand (0-255)
nn 16 bit operand (0-65535)
Zilog Mnemonics TDL Mnemonics (in forth format)
ADC A,(IX+d) d (X) ADC
ADC A,(IY+d) d (Y) ADC
ADC HL,BC B DADC
ADC HL,DE D DADC
ADC HL,HL H DADC
ADC HL,SP SP DADC
ADD A,(IX+d) d (X) ADD
ADD A,(IY+d) d (Y) ADD
ADD IX,BC B DADX
ADD IX,DE D DADX
ADD IX,IX X DADX
ADD IX,SP SP DADX
ADD IY,BC B DADY
ADD IY,DE D DADY
ADD IY,IY Y DADY
ADD IY,SP SP DADY
AND (IX+d) d (X) ANA
AND (IY+d) d (Y) ANA
BIT b,(HL) M b BIT
BIT b,(IX+d) d (X) b BIT
BIT b,(IY+d) d (Y) b BIT
BIT b,r r b BIT
CP (IX+d) d (X) CMP
CP (IY+d) d (Y) CMP
CPD CCD
CPDR CCDR
CPI CCI
CPIR CCIR
DEC (IX+d) d (X) DCR
DEC (IY+d) d (Y) DCR
DEC IX X DCX
DEC IY Y DCX
DJNZ nn nn DJNZ
EX (SP),IX XTIX
EX (SP),IY XTIY
EX AF,AF' EXAF
EXX EXX
IM 0 IM0
IM 1 IM1
IM 2 IM2
IN r,(C) r INP
INC (IX+d) d (X) INR
INC (IY+d) d (Y) INR
INC IX X INX
INC IY Y INX
IND IND
INDR INDR
INI INI
INIR INIR
JP (IX) PCIX
JP (IY) PCIY
JR nn nn JMPR
JR C,nn nn JRC
JR NC,nn nn JRNC
JR NZ,nn nn JRNZ
JR Z,nn nn JRZ
LD r,(IX+d) d (X) r MOV
LD r,(IY+d) d (Y) r MOV
LD (IX+d),r r d (X) MOV
LD (IY+d),r r d (Y) MOV
LD (IX+d),n n d (X) MVI
LD (IY+d),n n d (Y) MVI
LD (nn),BC nn SBCD
LD (nn),DE nn SDED
LD (nn),IX nn SIXD
LD (nn),IY nn SIYD
LD (nn),SP nn SSPD
LD A,I LDAI
LD A,R LDAR
LD I,A STAI
LD R,A STAR
LD BC,(nn) nn LBCD
LD DE,(nn) nn LDED
LD IX,nn nn X LXI
LD IY,nn nn Y LXI
LD IX,(nn) nn LIXD
LD IY,(nn) nn LIYD
LD SP,(nn) nn LSPD
LD SP,IX SPIX
LD SP,IY SPIY
LDD LDD
LDDR LDDR
LDI LDI
LDIR LDIR
NEG NEG
OR (IX+d) d (X) ORA
OR (IY+d) d (Y) ORA
OTDR OUTDR
OTIR OUTIR
OUT (C),r r OUTP
OUTD OUTD
OUTI OUTI
POP IX X POP
POP IY Y POP
PUSH IX X PUSH
PUSH IY Y PUSH
RES b,(HL) M b RES
RES b,(IX+d) d (X) b RES
RES b,(IY+d) d (Y) b RES
RES b,r r b RES
RETI RETI
RETN RETN
RL (HL) M RALR
RL (IX+d) d (X) RALR
RL (IY+d) d (Y) RALR
RL r r RALR
RLC (HL) M RLCR
RLC (IX+d) d (X) RLCR
RLC (IY+d) d (Y) RLCR
RLC r r RLCR
RLD RLD
RR (HL) M RARR
RR (IX+d) d (X) RARR
RR (IY+d) d (Y) RARR
RR r r RARR
RRC (HL) M RRCR
RRC (IX+d) d (X) RRCR
RRC (IY+d) d (Y) RRCR
RRC r r RRCR
RRD RRD
SBC A,(IX+d) d (X) SBB
SBC A,(IY+d) d (Y) SBB
SBC HL,BC B DSBC
SBC HL,DE D DSBC
SBC HL,HL H DSBC
SBC HL,SP SP DSBC
SET b,(HL) M b SET
SET b,(IX+d) d (X) b SET
SET b,(IY+d) d (Y) b SET
SET b,r r b SET
SLA (HL) M SLAR
SLA (IX+d) d (X) SLAR
SLA (IY+d) d (Y) SLAR
SLA r r SLAR
SRA (HL) M SRAR
SRA (IX+d) d (X) SRAR
SRA (IY+d) d (Y) SRAR
SRA r r SRAR
SRL (HL) M SRLR
SRL (IX+d) d (X) SRLR
SRL (IY+d) d (Y) SRLR
SRL r r SRLR
SUB (IX+d) d (X) SUB
SUB (IY+d) d (Y) SUB
XOR (IX+d) d (X) XRA
XOR (IX+d) d (X) XRA
6. References
F83 Forth v2.1.0 is a full-featured Forth package intended to run
under the CP/M 80 operating system. It conforms to the Forth-83
Standard. F83 is a public domain product and is available from many
sources including SIG/M Public Domain Catalog (Volume 204). Copies
of this disk should be available from SIG/M, P.O.Box 97 Iselin, New
Jersey 08830 USA or just about any CP/M bulletin board.