Labels:text | diagram | black and white | parallel | plan | schematic | number OCR: 23 Instruction Set Summary Instr Addressing Assembler Mode Format Operation Op Code Bytes Clock Hex Dec Cycles Status Register - P Instr ADC Immediate ADC #oper Zero Page .A+#+C -. A. C A + [addr] +C - . A. C 69 105 2 NVID 1 ADC addr 2 Z C ADC Zero Page. X 101 ADC addr. X .A + [addr +.X] + C -+ .A. C 65 75 2 3 - Absolute ADC ADDR A +[ADDR] +C - A. C 117 2 4 Absolute. X ADC ADDR. X A + [ADDR+X] + C -. A. C 6D 109 3 4 Absolute, Y ADC ADDR, Y 3 (Indirect. X) ADC (addr. X) .A+ [ADDR +.Y]+C -. A. C 7D 125 4 79 121 3 4. (Indirect). Y ADC (addr).Y A+[[addr+X+1, addr +.X]]+C -. A.C A+[[addr+1. addr] +Y]+C -. A. C 61 97 2 6 71 113 2 Ch AND Immediate AND #oper AN#- A N - Zero Page AND addr .A n [addr] - A 29 2 2 V Z C AND Zero Page, X A O [addr + .X] - . A 25 41 Absolute 35 37 2 AND addr. X 3 - - - ...
