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Text File  |  1996-04-29  |  11KB  |  200 lines
  1. Motorola 68000 Instruction Set.
  2. -------------------------------
  3.  
  4.                                                                Condition Codes
  5.                                                                ---------------
  6.                                           Assembler   Data
  7. Instruction Description                    Syntax     Size        X N Z V C
  8. -----------------------                   ---------   ----        ---------
  9.  
  10. ABCD     Add BCD with extend                Dx,Dy      B--        * U * U *
  11.                                          -(Ax),-(Ay)
  12. ADD      ADD binary                        Dn,<ea>     BWL        * * * * *
  13.                                            <ea>,Dn
  14. ADDA     ADD binary to An                  <ea>,An     -WL        - - - - -
  15. ADDI     ADD Immediate                     #x,<ea>     BWL        * * * * *
  16. ADDQ     ADD 3-bit immediate             #<1-8>,<ea>   BWL        * * * * *
  17. ADDX     ADD eXtended                       Dy,Dx      BWL        * * * * *
  18.                                          -(Ay),-(Ax)
  19. AND      Bit-wise AND                      <ea>,Dn     BWL        - * * 0 0
  20.                                            Dn,<ea>
  21. ANDI     Bit-wise AND with Immediate    #<data>,<ea>   BWL        - * * 0 0
  22. ASL      Arithmetic Shift Left            #<1-8>,Dy    BWL        * * * * *
  23.                                             Dx,Dy
  24.                                             <ea>
  25. ASR      Arithmetic Shift Right              ...       BWL        * * * * *
  26. Bcc      Conditional Branch            Bcc.S <label>   BW-        - - - - -
  27.                                        Bcc.W <label>
  28. BCHG     Test a Bit and CHanGe             Dn,<ea>     B-L        - - * - -
  29.                                         #<data>,<ea>
  30. BCLR     Test a Bit and CLeaR                ...       B-L        - - * - -
  31. BSET     Test a Bit and SET                  ...       B-L        - - * - -
  32. BSR      Branch to SubRoutine          BSR.S <label>   BW-        - - - - -
  33.                                        BSR.W <label>
  34. BTST     Bit TeST                          Dn,<ea>     B-L        - - * - -
  35.                                         #<data>,<ea>
  36. CHK      CHecK Dn Against Bounds           <ea>,Dn     -W-        - * U U U
  37. CLR      CLeaR                              <ea>       BWL        - 0 1 0 0
  38. CMP      CoMPare                           <ea>,Dn     BWL        - * * * *
  39. CMPA     CoMPare Address                   <ea>,An     -WL        - * * * *
  40. CMPI     CoMPare Immediate              #<data>,<ea>   BWL        - * * * *
  41. CMPM     CoMPare Memory                  (Ay)+,(Ax)+   BWL        - * * * *
  42. DBcc     Looping Instruction          DBcc Dn,<label>  -W-        - - - - -
  43. DIVS     DIVide Signed                     <ea>,Dn     -W-        - * * * 0
  44. DIVU     DIVide Unsigned                   <ea>,Dn     -W-        - * * * 0
  45. EOR      Exclusive OR                      Dn,<ea>     BWL        - * * 0 0
  46. EORI     Exclusive OR Immediate         #<data>,<ea>   BWL        - * * 0 0
  47. EXG      Exchange any two registers         Rx,Ry      --L        - - - - -
  48. EXT      Sign EXTend                         Dn        -WL        - * * 0 0
  49. ILLEGAL  ILLEGAL-Instruction Exception     ILLEGAL                - - - - -
  50. JMP      JuMP to Affective Address          <ea>                  - - - - -
  51. JSR      Jump to SubRoutine                 <ea>                  - - - - -
  52. LEA      Load Effective Address            <ea>,An     --L        - - - - -
  53. LINK     Allocate Stack Frame       An,#<displacement>            - - - - -
  54. LSL      Logical Shift Left                 Dx,Dy      BWL        * * * 0 *
  55.                                           #<1-8>,Dy
  56.                                             <ea>
  57. LSR      Logical Shift Right                 ...       BWL        * * * 0 *
  58. MOVE     Between Effective Addresses      <ea>,<ea>    BWL        - * * 0 0
  59. MOVE     To CCR                           <ea>,CCR     -W-        I I I I I
  60. MOVE     To SR                             <ea>,SR     -W-        I I I I I
  61. MOVE     From SR                           SR,<ea>     -W-        - - - - -
  62. MOVE     USP to/from Address Register      USP,An      --L        - - - - -
  63.                                            An,USP
  64. MOVEA    MOVE Address                      <ea>,An     -WL        - - - - -
  65. MOVEM    MOVE Multiple            <register list>,<ea> -WL        - - - - -
  66.                                   <ea>,<register list>
  67. ---------- Page 2. CUT HERE. ----------
  68. MOVEP    MOVE Peripheral                  Dn,x(An)     -WL        - - - - -
  69.                                           x(An),Dn
  70. MOVEQ    MOVE 8-bit immediate         #<-128.+127>,Dn  --L        - * * 0 0
  71. MULS     MULtiply Signed                   <ea>,Dn     -W-        - * * 0 0
  72. MULU     MULtiply Unsigned                 <ea>,Dn     -W-        - * * 0 0
  73. NBCD     Negate BCD                         <ea>       B--        * U * U *
  74. NEG      NEGate                             <ea>       BWL        * * * * *
  75. NEGX     NEGate with eXtend                 <ea>       BWL        * * * * *
  76. NOP      No OPeration                        NOP                  - - - - -
  77. NOT      Form one's complement              <ea>       BWL        - * * 0 0
  78. OR       Bit-wise OR                       <ea>,Dn     BWL        - * * 0 0
  79.                                            Dn,<ea>
  80. ORI      Bit-wise OR with Immediate     #<data>,<ea>   BWL        - * * 0 0
  81. PEA      Push Effective Address             <ea>       --L        - - - - -
  82. RESET    RESET all external devices         RESET                 - - - - -
  83. ROL      ROtate Left                      #<1-8>,Dy    BWL        - * * 0 *
  84.                                             Dx,Dy
  85.                                             <ea>
  86. ROR      ROtate Right                        ...       BWL        - * * 0 *
  87. ROXL     ROtate Left with eXtend             ...       BWL        * * * 0 *
  88. ROXR     ROtate Right with eXtend            ...       BWL        * * * 0 *
  89. RTE      ReTurn from Exception               RTE                  I I I I I
  90. RTR      ReTurn and Restore                  RTR                  I I I I I
  91. RTS      ReTurn from Subroutine              RTS                  - - - - -
  92. SBCD     Subtract BCD with eXtend           Dx,Dy      B--        * U * U *
  93.                                          -(Ax),-(Ay)
  94. Scc      Set to -1 if True, 0 if False      <ea>       B--        - - - - -
  95. STOP     Enable & wait for interrupts      #<data>                I I I I I
  96. SUB      SUBtract binary                   Dn,<ea>     BWL        * * * * *
  97.                                            <ea>,Dn
  98. SUBA     SUBtract binary from An           <ea>,An     -WL        - - - - -
  99. SUBI     SUBtract Immediate                #x,<ea>     BWL        * * * * *
  100. SUBQ     SUBtract 3-bit immediate       #<data>,<ea>   BWL        * * * * *
  101. SUBX     SUBtract eXtended                  Dy,Dx      BWL        * * * * *
  102.                                          -(Ay),-(Ax)
  103. SWAP     SWAP words of Dn                    Dn        -W-        - * * 0 0
  104. TAS      Test & Set MSB & Set N/Z-bits      <ea>       B--        - * * 0 0
  105. TRAP     Execute TRAP Exception           #<vector>               - - - - -
  106. TRAPV    TRAPV Exception if V-bit Set       TRAPV                 - - - - -
  107. TST      TeST for negative or zero          <ea>       BWL        - * * 0 0
  108. UNLK     Deallocate Stack Frame              An                   - - - - -
  109.  
  110.                            --------------------------
  111.  
  112. Symbol   Meaning
  113. ------   -------
  114.  
  115.    *     Set according to result of operation
  116.    -     Not affected
  117.    0     Cleared
  118.    1     Set
  119.    U     Outcome (state after operation) undefined
  120.    I     Set by immediate data
  121.  
  122. <ea>     Effective Address Operand
  123. <data>   Immediate data
  124. <label>  Assembler label
  125. <vector> TRAP instruction Exception vector (0-15)
  126. <rg.lst> MOVEM instruction register specification list
  127. <displ.> LINK instruction negative displacement
  128. ...      Same as previous instruction
  129.  
  130.                            --------------------------
  131. ---------- Page 3. CUT HERE. ----------
  132. Addressing Modes                                   Syntax
  133. ----------------                                   ------
  134.  
  135. Data Register Direct                                 Dn
  136. Address Register Direct                              An
  137. Address Register Indirect                           (An)
  138. Address Register Indirect with Post-Increment       (An)+
  139. Address Register Indirect with Pre-Decrement        -(An)
  140. Address Register Indirect with Displacement         w(An)
  141. Address Register Indirect with Index               b(An,Rx)
  142. Absolute Short                                        w
  143. Absolute Long                                         l
  144. Program Counter with Displacement                   w(PC)
  145. Program Counter with Index                         b(PC,Rx)
  146. Immediate                                            #x
  147. Status Register                                      SR
  148. Condition Code Register                              CCR
  149.  
  150. Legend
  151. ------
  152.    Dn    Data Register        (n is 0-7)
  153.    An    Address Register     (n is 0-7)
  154.     b    08-bit constant
  155.     w    16-bit constant
  156.     l    32-bit constant
  157.     x    8-, 16-, 32-bit constant
  158.    Rx    Index Register Specification, one of:
  159.             Dn.W  Low 16 bits of Data Register
  160.             Dn.L  All 32 bits of Data Register
  161.             An.W  Low 16 bits of Address Register
  162.             An.L  All 32 bits of Address Register
  163.  
  164.                            --------------------------
  165.  
  166.          Condition Codes for Bcc, DBcc and Scc Instructions.
  167.          ---------------------------------------------------
  168.  
  169.            Condition Codes set after CMP D0,D1 Instruction.
  170.  
  171. Relationship      Unsigned                         Signed
  172. ------------      --------                         ------
  173.  
  174. D1 <  D0          CS - Carry Bit Set               LT - Less Than
  175. D1 <= D0          LS - Lower or Same               LE - Less than or Equal
  176. D1  = D0          EQ - Equal (Z-bit Set)           EQ - Equal (Z-bit Set)
  177. D1 != D0          NE - Not Equal (Z-bit Clear)     NE - Not Equal (Z-bit Clear)
  178. D1 >  D0          HI - HIgher than                 GT - Greater Than
  179. D1 >= D0          CC - Carry Bit Clear             GE - Greater than or Equal
  180.  
  181.                   PL - PLus (N-bit Clear)          MI - Minus (N-bit Set)
  182.                   VC - V-bit Clear (No Overflow)   VS - V-bit Set (Overflow)
  183.                   RA - BRanch Always
  184.  
  185. DBcc Only    -     F - Never Terminate (DBRA is an alternate to DBF)
  186.                    T - Always Terminate
  187.  
  188. Scc Only     -    SF - Never Set
  189.                   ST - Always Set
  190.  
  191.                            --------------------------
  192.  
  193. Parts from "Programming the 68000" by Steve Williams. (c) 1985 Sybex Inc.
  194. Parts from BYTE Magazine article.
  195.  
  196. Compiled by Diego Barros.        e-mail : alien@zikzak.apana.org.au
  197. Revision 2.1                     22 May, 1994
  198. ---------- Last Page. CUT HERE. ----------
  199.  
  200.