The DG-5 is a dynamic display type frequency counter. All this means is that fewer wires and decode drivers are needed for frequency display.
We shall start the xplanation of the DG-5 with the reference oscillator Q21. This circuit provides the timing pulses, calibration and scanning pulses for operation of the DG-5. The ten MHz reference oscillator is divided 1/10 by IC5 to provide calibrated one MHz output. It is then further divided by IC6 and IC7 1/100. The divided signal is then passed thru IC8 which consists of two sections, a 1/5 and 1/2 divider. The divide by 1/5 section now gives a resultant 2 kHz signal on its output. This is the scanning pulse. IC40 receives the scanning puse wwhich gives an output in a modified BCD code. The IC41 which is a decode driver (Neg. Logic Type) is used to switch Q25-30 via terminals T1-T6 to put a plus voltage on display D1-D3 (LED Type).
At the same time, outputs T1-6 of IC41 are inverted by IC42 positivie logic and the BCD information is presented to IC32-37 the and-or-invert gats which provide the conditional inputs for the multiplexer or distributro. IC38 provides Negative logic inversion for IC39 the decode driver.
The multiplexer information starts with the heterodyne of the three components, reference oscillator, carrier and VFO input signals.
IC26-31 are the multiplexer inputs. These are latches wshich store BCD information until they are told to release their output by IC3 the strobe or latch signal.
I will mention now, that if the HET or VFO input signal are absent, that the blanking circuits will take effect. At this time the HET input is amplified and is shaped by the Schmidt trigger IC1. The carrier output is then mixed with the balance mixer Q16 and Q17. Its output is then mixed again with VFO and its output appears on Q18 drain. Its buffered by Q19 and shaped by IC2B. This output is placed on timing window IC2C. Two signals are presented to the timing window: 1) signal to be measured, 2) gating signal .1 sec. in length (IC11 pin 8.)
The DG-5 contains two window circuits IC2C and IC1C. IC1C forms the HET counter window circuit and IC2 forms the preset counter circuit.
With a gate signal the HET counter begins to count the pulses which pass thru the gate, and so does the preset counter circuit. the outputs of the timing windows are a ratio of signal input divided by gate pulse. Example, with a .1 sec. gating pulse the display would be updated once every .2 sec. period. If a 1.2 MHz input was measured, the display would read "1200" in KHz. The gated output information of IC1C is then distributed on the HET counters IC12-18. At this time it should be realized that IC41 the decode driver is used merely to supply a plus voltage to display and is controlled by 2KHz scanning pulse. IC2D is gated with the same .1 sec. pulse and the output signal ito be measured is the rario of signal input (VFO, REF and Carrier) divided by gate pulse.
Doth HET and preset BCD information is presented to latch circuits which is then sent to decode driver IC39 for display information. Since only one decode driver is being used for all displays, the conditional inputs of IC32-37 must be turned "ON" and "OFF" quickly in order not to be detectable by the human eye. This is done easily by the high speed TTL circuits.
Note: The display scheme of the DG-1 and DG-5 are esentially the same. The theory of operation is therefore applicable to the DG-1 Display as well.
(c) 2378TKC
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