Labels:text | diagram | rectangle | plan | schematic | parallel OCR: 4-Mbit SRAM Core Processor Two independent 2-Mbit banks Timer Cache dual ported JTAG Procossor Port TO Port Addr Data Data Ador Test and Emulation DAG 1 DAG 2 Program Sequencer PM Address Bus 24 External Port DM Address Bus 82. Address BUS MUX Host Port and Multiprocessor PM Data Bus 48 Interface Connect DM Data Bus 40 Data Bus MUX DMA Register IOP. Control File 16%40 Register Serial Ports Muhipler Barrel {Memory Shifter ALU Mapper Line Ports 0.1.2.3.4.5 WO Processor Figure 1: ADSP-21060 block diagram.
