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Developer Source 3
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Developers_Source_Vol_03_1996.iso
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dobbs
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nov95
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may0f103.gif
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Graphics Interchange Format
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1996-06-12
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75KB
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504x450
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4-bit (16 colors)
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OCR:
Packet Src Mux Transfer FIFO Dst Mux and and Alignment Cache Alignment Buffer External 64 Internal Memory Memory 64 Interface Interface Source Destination Controller Cache, Controller VRAM, and Source- Refresh Destination- Control Controller Control Registers Registers Request Queuing and Prioritization Logic MP Cache ADSP VC External Host Requests Cache Requests Packet Requests Requests Transfer Requests Figure 3: Transfer controller.
