home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
Fujiology Archive
/
fujiology_archive_v1_0.iso
/
!MAGS
/
MEGA_4
/
MEGAFOUR.ZIP
/
MEGAFOUR.MSA
/
DOCS
/
17.DOC
< prev
next >
Wrap
Text File
|
1985-11-20
|
40KB
|
870 lines
****************************************************************************
* *
* *
* ===================================================================== *
* A T A R I - F A L C O N - H A R D W A R E - R E G I S T E R S *
* ===================================================================== *
* *
* *
* T R Y O F D O C U M E N T A T I O N B Y *
* *
* A E O N & C H R I S *
* *
* O F A U R A *
* *
* VERSION 0.4 (11.04.93) *
* *
* FIRST OFFICIAL RELEASE *
* *
****************************************************************************
For any questions and donations write to:
AURA
PLK 019200 C
W-7600 OFFENBURG
GERMANY
If you have found some new things about the hardware just contact us.
Don't forget to include international reply coupons if you expect an
answer.
Remember:
Donations will force us to release more informations about the hardware.
signing: AEON/CHRIS OF AURA
----------------------------------------------------------------------------
******: seems to be unused
new : new FALCON-adresses
new<==: perhaps new FALCON registers
<=====: new FALCON registers
****************************************************************************
I D E - P O R T ( F A L C O N )
****************************************************************************
$FFF00000 [R/W] :$?? <=====
: : :
: : :
$FFF0003F [R/W] :$?? <=====
****************************************************************************
M E M O R Y - M A N A G E M E N T ( S T )
****************************************************************************
$FFFF8000 [R/W] :$8F ******
$FFFF8001 [R/W] :$00 Memory-Configuration
****************************************************************************
? ? ?
****************************************************************************
$FFFF8006 [R/W] :$56 76______................................Monitor-Type Hi
||
00 --------- SM124 and compatible
01 --------- SC1435 and compatible
10 --------- VGA and SYNC-monitors
11 --------- TV
$FFFF8007 [R/W] :$65 <=====
$FFFF800C [R/W] :$8F ******
$FFFF800D [R/W] :$00 <=====
****************************************************************************
V I D E O - S Y S T E M ( F A L C O N )
****************************************************************************
$FFFF8200 [R/W] :$8F ******
$FFFF8201 [R/W] :$3F Video-Address Hi
$FFFF8202 [R/W] :$8F ******
$FFFF8203 [R/W] :$82 Video-Address Mi
$FFFF8204 [R/W] :$8F ******
$FFFF8205 [R/W] :$3F Video-Address-Counter Hi
$FFFF8206 [R/W] :$8F ******
$FFFF8207 [R/W] :$AB Video-Address-Counter Mi
$FFFF8208 [R/W] :$8F ******
$FFFF8209 [R/W] :$D2 Video-Address-Counter Lo
$FFFF820A [R/W] :$02 ______10 ..................................... Syncmode
||
|+----- 1: external clock
| 0: internal clock
+------ set to one (ex-50/60 Hz-Bit)
$FFFF820B [R/W] :$00 ******
$FFFF820C [R/W] :$8F ******
$FFFF820D [R/W] :$00 Video-Address Lo
$FFFF820E [R/W] :$00 _______0 ................................. Line-Wide Hi
$FFFF820F [R/W] :$00 76543210 ................................. Line-Wide Lo
This register is used to configure the
worddistanz from the end of one to the
beginning of the next graphic line.
Example: $0050 adds 80 words (160 bytes) after
every line to the Videoaddress.
$FFFF8210 [R/W] :$00 ______10 ............................. Vertical-Wrap Hi
$FFFF8211 [R/W] :$50 76543210 ..............................Vertical-Wrap Lo
This register is used to configure the
wordlengh of one graphic line.
Example: ST-Low : $0050= 80 words
256 Colors/640x200: $0140=320 words
True-Color/320x400: $0140=320 words
$FFFF8212 [R/W] :$8F ******
: : : :
: : : :
$FFFF823F [R/W] :$6A ******
$FFFF8240 [R/W] :$0F ST Color $00 Hi
$FFFF8241 [R/W] :$0F Lo
$FFFF8242 [R/W] :$0F ST Color $01 Hi
$FFFF8243 [R/W] :$0F Lo
$FFFF8244 [R/W] :$00 ST Color $02 Hi
$FFFF8245 [R/W] :$00 Lo
$FFFF8246 [R/W] :$00 ST Color $03 Hi
$FFFF8247 [R/W] :$00 Lo
$FFFF8248 [R/W] :$00 ST Color $04 Hi
$FFFF8249 [R/W] :$00 Lo
$FFFF824A [R/W] :$0F ST Color $05 Hi
$FFFF824B [R/W] :$0F Lo
$FFFF824C [R/W] :$00 ST Color $06 Hi
$FFFF824D [R/W] :$00 Lo
$FFFF824E [R/W] :$0D ST Color $07 Hi
$FFFF824F [R/W] :$0D Lo
$FFFF8250 [R/W] :$04 ST Color $08 Hi
$FFFF8251 [R/W] :$04 Lo
$FFFF8252 [R/W] :$05 ST Color $09 Hi
$FFFF8253 [R/W] :$05 Lo
$FFFF8254 [R/W] :$00 ST Color $0A Hi
$FFFF8255 [R/W] :$00 Lo
$FFFF8256 [R/W] :$05 ST Color $0B Hi
$FFFF8257 [R/W] :$05 Lo
$FFFF8258 [R/W] :$00 ST Color $0C Hi
$FFFF8259 [R/W] :$00 Lo
$FFFF825A [R/W] :$05 ST Color $0D Hi
$FFFF825B [R/W] :$05 Lo
$FFFF825C [R/W] :$00 ST Color $0E Hi
$FFFF825D [R/W] :$00 Lo
$FFFF825E [R/W] :$00 ST Color $0F Hi
$FFFF825F [R/W] :$00 Lo
$FFFF8260 [R/W] :$01 ______10 ..................................... ST-Shift
||
00---- ST-Lowres
01---- ST-Medres
10---- ST-Highres
11---- not defined
$FFFF8261 [R/W] :$00 ******
$FFFF8262 [R/W] :$00 ******
$FFFF8263 [R/W] :$00 ******
$FFFF8264 [R/W] :$00 ________ ..........................Horizontal-Scroll Hi
$FFFF8265 [R/W] :$00 ____3210 ..........................Horizontal-Scroll Lo
||||
++++---- 0-15: left shifted pixel
$FFFF8266 [R/W] :$00 _____2_0 .............................. Falcon-Shift Hi
| |
| +---- 1: True-color mode
+------ 1: 2-color mode
$FFFF8267 [R/W] :$00 _654____ ...............................Falcon-Shift Lo
|||
||+-------- 1: 256-color mode
|+--------- 0: internal vertical sync
| 1: external vertical sync
+---------- 0: internal horizontal sync
1: external horizontal sync
$FFFF8268 [R/W] :$00 ******
: : : :
: : : :
$FFFF827F [R/W] :$00 ******
$FFFF8280 [R/W] :$00 ______10 ................... Horizontal-hold-counter Hi
$FFFF8281 [R/W] :$0F 76543210 ................... Horizontal-hold-counter Lo
You can only read this register.
$FFFF8282 [R/W] :$00 ______10 ..................... Horizontal-hold-timer Hi
$FFFF8283 [R/W] :$00 76543210 ..................... Horizontal-hold-timer Lo
$FFFF8284 [R/W] :$00 ______10 ................... Horizontal-border-begin Hi
$FFFF8285 [R/W] :$00 76543210 ................... Horizontal-border-begin Lo
$FFFF8286 [R/W] :$00 ______10 ..................... Horizontal-border-end Hi
$FFFF8287 [R/W] :$00 76543210 ..................... Horizontal-border-end Lo
$FFFF8288 [R/W] :$02 ______10 .................. Horizontal-display-begin Hi
$FFFF8289 [R/W] :$02 76543210 .................. Horizontal-display-begin Lo
$FFFF828A [R/W] :$00 ______10 .................... Horizontal-display-end Hi
$FFFF828B [R/W] :$00 76543210 .................... Horizontal-display-end Lo
$FFFF828C [R/W] :$00 ______10 ............................. Horizontal-SS Hi
$FFFF828D [R/W] :$00 76543210 ............................. Horizontal-SS Lo
$FFFF828E [R/W] :$00 _______0 ............................. Horizontal-FS Hi
$FFFF828F [R/W] :$00 76543210 ............................. Horizontal-FS Lo
$FFFF8290 [R/W] :$00 _______0 ............................. Horizontal-HH Hi
$FFFF8291 [R/W] :$00 76543210 ............................. Horizontal-HH Lo
$FFFF8292 [R/W] :$00 ******
: : : :
: : : :
$FFFF829F [R/W] :$00 ******
$FFFF82A0 [R/W] :$01 _____210 ................. Vertical-frequenz-counter Hi
$FFFF82A1 [R/W] :$9C 76543210 ................. Vertical-freuqenz-counter Lo
You can only read this register.
$FFFF82A2 [R/W] :$02 _____210 ................... Vertical-frequenz-timer Hi
$FFFF82A3 [R/W] :$02 76543210 ................... Vertical-frequenz-timer Lo
$FFFF82A4 [R/W] :$02 _____210 ..................... Vertical-border-begin Hi
$FFFF82A5 [R/W] :$02 76543210 ..................... Vertical-border-begin Lo
$FFFF82A6 [R/W] :$00 _____210 ....................... Vertical-border-end Hi
$FFFF82A7 [R/W] :$00 76543210 ....................... Vertical-border-end Lo
$FFFF82A8 [R/W] :$00 _____210 .................... Vertical-display-begin Hi
$FFFF82A9 [R/W] :$00 76543210 .....................Vertical-display-begin Lo
$FFFF82AA [R/W] :$01 _____210 .......................Vertical-display-end Hi
$FFFF82AB [R/W] :$01 76543210 .......................Vertical-display-end Lo
$FFFF82AC [R/W] :$02 _____210 ................................Vertical-SS Hi
$FFFF82AD [R/W] :$02 76543210 ................................Vertical-SS Lo
$FFFF82AE [R/W] :$00 ******
: : : :
: : : :
$FFFF82BF [R/W] :$00 ******
$FFFF82C0 [R/W] :$00 <===== Hi
$FFFF82C1 [R/W] :$00 <===== Lo
$FFFF82C2 [R/W] :$00 ________ ............................. Video-Control Hi
$FFFF82C3 [R/W] :$00 _____21_ ............................. Video-Control Lo
||
|+----- 1: interlace on
+------ 0: 320 pixel horizontal
1: 640 pixel horizontal
****************************************************************************
D M A / D I S K - C O N T R O L L E R ( S T )
****************************************************************************
$FFFF8604 [R/W] :$00A0 FDC / Sektor Count
$FFFF8606 [R/-] :$0001 DMA Status
[-/W] :$0001 DMA Mode
$FFFF8608 [R/W] :$00 ******
$FFFF8609 [R/-] :$00 Count Hi
[-/W] :$00 DMA Base Hi
$FFFF860A [R/W] :$00 ******
$FFFF860B [R/-] :$20 Count Mi
[-/W] :$20 DMA Base Mi
$FFFF860C [R/W] :$00 ******
$FFFF860D [R/-] :$C6 Count Lo
[-/W] :$C6 DMA Base Lo
$FFFF860E [R/W] :$00 <=====
$FFFF860F [R/W] :$80 <=====
****************************************************************************
P S G - S O U N D C H I P AY-3-8910 ( S T )
****************************************************************************
$FFFF8800 [R/-] :$67 Read Data
[-/W] :$67 Register Selection
$FFFF8801 [R/W] :$FF ******
$FFFF8802 [R/W] :$CF Write Data
$FFFF8803 [R/W] :$FF ******
NOTE: The PSG-Registers are now fixed at 2 addresses($8800.w/$8802.w).
Accessing the shadowregisters ($8804.w-$8900.w) cause a buserror.
****************************************************************************
P C M - S O U N D C H I P ( C O D E C )
****************************************************************************
$FFFF8900 [R/W] :$05 ____3210 ......................... Sound-DMA-Control Hi
||||
|||| MFP-IRQ-7
||00---- no request
||01---- after playing a frame
||10---- after recording a frame
||11---- after playing or recording a frame
||
|| Timer-A-Request
00------ no request
01------ after playing a frame
10------ after recording a frame
11------ after playing or recording a frame
$FFFF8901 [R/W] :$00 7_54__10 ......................... Sound-DMA-Control Lo
| || ||
| || |+---- 1: DMA-Play enable
| || +----- 1: DMA-Play frame repeat
| |+-------- 1: DMA-Record enable
| +--------- 1: DMA-Record frame repeat
+----------- 0: select playframe-adresses
1: select recordfame-adresses
..................................Frame-Addresses
$FFFF8902 [R/W] :$00 ******
$FFFF8903 [R/W] :$01 Frame-Start-Address Hi
$FFFF8904 [R/W] :$00 ******
$FFFF8905 [R/W] :$29 Frame-Start-Address Mi
$FFFF8906 [R/W] :$00 ******
$FFFF8907 [R/W] :$9C Frame-Start-Address Lo
$FFFF8908 [R/W] :$00 ******
$FFFF8909 [R/W] :$01 Frame-Address-Counter Hi
$FFFF890A [R/W] :$00 ******
$FFFF890B [R/W] :$29 Frame-Address-Counter Mi
$FFFF890C [R/W] :$00 ******
$FFFF890D [R/W] :$9C Frame-Address-Counter Lo
$FFFF890E [R/W] :$00 ******
$FFFF890F [R/W] :$02 Frame-End-Address Hi
$FFFF8910 [R/W] :$00 ******
$FFFF8911 [R/W] :$B0 Frame-End-Address Mi
$FFFF8912 [R/W] :$00 ******
$FFFF8913 [R/W] :$3C Frame-End-Address Lo
HOW to access the play/record-frame:
You have to set bit 7 of $8901.w to select play- or record-shadowregister,
then access the frame-begin/end-registers! The play- and record-shadow-
register are two seperate registers; they appear only at the same
addresses!
$FFFF8920 [R/W] :$00 __54__10 ........................... Track-Play-Control
|| ||
|| 00---- play 1 track
|| 01---- play 2 tracks
|| 10---- play 3 tracks
|| 11---- play 4 tracks
00 ------- connect track 1 with speaker
01 ------- connect track 2 with speaker
10 ------- connect track 3 with speaker
11 ------- connect track 4 with speaker
$FFFF8921 [R/W] :$03 76____10 ........................... Sound-Mode-Control
|| ||
|| 00---- nute condition (on STE: 6258 Hz)
|| 01---- 12517 HZ
|| 10---- 25033 HZ
|| 11---- 50066 HZ
|+---------- 0: 8 Bit
| 1: 16 Bit
+----------- 0: Stereo
1: Mono
Nice to know: The samplerate 6258 Hz was repleaced by a nute condition.
You can use it to deactivate the DMA-Transfer.
$FFFF8922 [R/-] :$00 not accessed by the XBIOS.
$FFFF8923 [R/-] :$00 The FALCON has no
$FFFF8924 [R/-] :$00 Microwire-
$FFFF8925 [R/-] :$00 Interface!!
$FFFF8930 [R/W] :$01 76543210 ......... Sound-Source-Device-Prescale-Mode Hi
||||||||
|||||||| Source-Device: EXT-INP
|||||||+---- 1: Handshaking off
|||||++----- Source-Clock
||||+------- set to zero
||||
|||| Source-Device: A/D-Converter
|||+-------- set to zero
||+--------- 0: internal 25.175 MHz-Clock
|| 1: extermal Clock
++---------- set to zero
$FFFF8931 [R/W] :$11 76543210 ......... Sound-Source-Device-Prescale-Mode Lo
||||||||
|||||||| Source-Device: DMA-PLAY
|||||||+---- 1: Handshaking off
|||||++----- Source-Clock
||||+------- 0: if handshaking on and destination=
|||| DSP-REC
|||| 1: if destination<>DSP-REC
|||| (this allows a automatic transfer from
|||| (memory to DSP without errors.)
||||
|||| Source-Device: DSP-XMIT
|||+-------- 1: Handshaking off
|++--------- Source-Clock
+----------- 0: Tristate, disconnect DSP from Multi-
plexer (only if you want to use the
external SSI-Port)
1: connect DSP with Multiplexer
Source-Clock can be : %00: internal 25.175 MHz-Clock
%01: external Clock
%10: intermal 32 MHz-Clock,do not use it for the
CODEC (A/D- and D/A-Converter).
%11: not defined
$FFFF8932 [R/W] :$00 76543210 ........... Sound-Destination-Device-Matrix Hi
||||||||
|||||||| Source-Device for destination: EXT-OUT
|||||||+---- 1: Handshaking off
|||||++----- Source-Device
||||+------- set to zero
||||
|||| Source-Device for destination: DAC
|||+-------- set to zero
|++--------- Source-Device
+----------- set to zero
$FFFF8933 [R/W] :$00 76543210 ........... Sound-Destination-Device-Matrix Lo
||||||||
|||||||| Source-Device for destination: DMA-REC
|||||||+---- 1: Handshaking off
|||||++----- Source-Device
||||+------- 0: if handshaking on and source=DSP-XMIT
|||| 1: if source<>DSP-XMIT
|||| (this modus allows a automatic transfer
|||| from DSP to memory without errors.)
||||
|||| Source-Device for destination: DSP-REC
|||+-------- 1: Handshaking off
|++--------- Source-Device
+----------- 0: Tristate, disconnect DSP from Multi-
plexer (only if you want to use the
external SSI-Port)
1: connect DSP with Multiplexer
Source-Device can be: %00: DMA-PLAY
%01: DSP-XMIT (DSP send data)
%10: EXT-INP (External Input)
%11: A/D-Converter
$FFFF8934 [R/W] :$00 ____3210 ...................... Prescale external Clock
||||
++++---- 0: switch to STE-compatible mode
1-15: Clock devided by 256, devided by
prescalevalue+1.
Documentation only allows values between
0 and 15, but the XBIOS allows values
between 0 and 255. The upper nibble is
cut by the hardware.
$FFFF8935 [R/W] :$01 ____3210 ... Prescale internal Clock (25.175 or 32 MHz)
||||
++++---- look above! According to the
|||| Documentation you can only use the
|||| following values for the CODEC(A/D- and
|||| D/A-Converter): 0,1,2,3,4,5,7,9,11
0000---- switch to STE-compatible mode
0001---- CLK50K 49170 Hz
0010---- CLK33K 32780 Hz
0011---- CLK25K 24585 Hz
0100---- CLK20K 19668 Hz
0101---- CLK16K 16390 Hz
0110---- CLK14K 14049 Hz (invalid for CODEC)
0111---- CLK12K 12292 Hz
1000---- CLK11K 10927 Hz (invalid for CODEC)
1001---- CLK10K 9834 Hz
1010---- CLK09K 8940 Hz (invalid for CODEC)
1011---- CLK08K 8195 Hz
1100---- CLK07K 7565 Hz (invalid for CODEC)
1101---- CLK07K 7024 Hz (invalid for CODEC)
1110---- CLK06K 6556 Hz (invalid for CODEC)
1111---- CLK06K 6146 HZ (invalid for CODEC)
$FFFF8936 [R/W] :$00 ______10 ......................... Track-Record-Control
||
00---- record 1 track
01---- record 2 tracks
10---- record 3 tracks
11---- record 4 tracks
$FFFF8937 [R/W] :$03 ______10 .................... CODEC-Hardwareadder-Input
|| (ADDRIN-register)
|| Source-input of the 16-bit-hardwareadder
||
|+---- 1: input from A/D-Converter
+----- 1: input from Multiplexer
NOTE: The CODEC-Hardwareadder-Input connects the D/A-Converter with the
multiplexer or the A/D-Converter. It is also possible to connect both.
In this case the 16-bit-Hardwareadder mix the two signals.
$FFFF8938 [R/W] :$03 ______10 .......................... A/D-Converter-Input
|| (ADCINPUT-register)
|+---- 0: input from right mic-channel
| 1: input from right PSG-channel
+----- 0: input from left mic-channel
1: input from left PSG-channel
$FFFF8939 [R/W] :$88 76543210 ..... Channel-Input-Amplifier in +1.5 dB steps
|||||||| (GAIN-register)
||||||||
||||++++---- 0-15: Gain right channel (RTGAIN)
++++-------- 0-15: Gain of left channel (LTGAIN)
$FFFF893A [R/W] :$07 ____3210 . Channel-Output-Amplifier in -1.5 dB-steps Hi
|||| (ATTEN-register)
||||
++++---- 0-15: Attenuation of feft channal(LTATTEN)
$FFFF893B [R/W] :$70 7654____ ........................................... Lo
||||
++++------- 0-15: Attenuation of right channel(RTATTEN)
$FFFF893C [R/W] :$64 ______10 .............................. CODEC-Status Hi
||
|+---- 1: right channel-overflow
+----- 1: left channel-overflow
$FFFF893D [R/W] :$00 7654____ .............................. CODEC-Status Lo
||||
|||+------ ?
||+------- ?
|+-------- ?
+--------- ?
$FFFF893E [R/W] :$81 not accessed
$FFFF893F [R/W] :$00 by the XBIOS
$FFFF8940 [R/W] :$00 <===== Hi
$FFFF8941 [R/W] :$00 _____210 ..............................GPx-Dataportpath
|||
+++---- bidirectional Dataportpath of the GP0-
GP2-Pins on the DSP-Connector
0: Pin set to Input (read data from GPx)
1: Pin set to Output (write data to GPx)
(normally %111)
$FFFF8942 [R/W] :$00 <===== Hi
$FFFF8943 [R/W] :$07 _____210 ................................. GPx-Dataport
|||
+++---- Input/Output-Data-Bits of the
GP0-GP2-Pins on the DSP-Connector. This
Pins can be used for userdef. operations.
****************************************************************************
C L O C K - C H I P ( T T )
****************************************************************************
$FFFF8960 [R/W] :$DF ******
$FFFF8961 [R/W] :$FF Register Selection
$FFFF8962 [R/W] :$DF ******
$FFFF8963 [R/W] :$FF Data
****************************************************************************
B L I T T E R ( S T E )
****************************************************************************
$FFFF8A00 [R/W] :$FF Halftone RAM $00 Hi
$FFFF8A01 [R/W] :$FF Lo
$FFFF8A02 [R/W] :$FF Halftone RAM $01 Hi
$FFFF8A03 [R/W] :$FF Lo
$FFFF8A04 [R/W] :$FF Halftone RAM $02 Hi
$FFFF8A05 [R/W] :$FF Lo
$FFFF8A06 [R/W] :$FF Halftone RAM $03 Hi
$FFFF8A07 [R/W] :$FF Lo
$FFFF8A08 [R/W] :$FF Halftone RAM $04 Hi
$FFFF8A09 [R/W] :$FF Lo
$FFFF8A0A [R/W] :$FF Halftone RAM $05 Hi
$FFFF8A0B [R/W] :$FF Lo
$FFFF8A0C [R/W] :$FF Halftone RAM $06 Hi
$FFFF8A0D [R/W] :$FF Lo
$FFFF8A0E [R/W] :$FF Halftone RAM $07 Hi
$FFFF8A0F [R/W] :$FF Lo
$FFFF8A10 [R/W] :$FF Halftone RAM $08 Hi
$FFFF8A11 [R/W] :$FF Lo
$FFFF8A12 [R/W] :$FF Halftone RAM $09 Hi
$FFFF8A13 [R/W] :$FF Lo
$FFFF8A14 [R/W] :$FF Halftone RAM $0A Hi
$FFFF8A15 [R/W] :$FF Lo
$FFFF8A16 [R/W] :$FF Halftone RAM $0B Hi
$FFFF8A17 [R/W] :$FF Lo
$FFFF8A18 [R/W] :$FF Halftone RAM $0C Hi
$FFFF8A19 [R/W] :$FF Lo
$FFFF8A1A [R/W] :$FF Halftone RAM $0D Hi
$FFFF8A1B [R/W] :$FF Lo
$FFFF8A1C [R/W] :$FF Halftone RAM $0E Hi
$FFFF8A1D [R/W] :$FF Lo
$FFFF8A1E [R/W] :$FF Halftone RAM $0F Hi
$FFFF8A1F [R/W] :$FF Lo
$FFFF8A20 [R/W] :$00 Source-X-Increment Hi
$FFFF8A21 [R/W] :$00 Lo
$FFFF8A22 [R/W] :$FF Source-Y-Increment Hi
$FFFF8A23 [R/W] :$00 Lo
$FFFF8A24 [R/W] :$00 ******
$FFFF8A25 [R/W] :$E4 Source-Address Hi
$FFFF8A26 [R/W] :$89 Mi
$FFFF8A27 [R/W] :$6C Lo
$FFFF8A28 [R/W] :$FF End-Mask 1 Hi
$FFFF8A29 [R/W] :$FF Lo
$FFFF8A2A [R/W] :$FF End-Mask 2 Hi
$FFFF8A2B [R/W] :$FF Lo
$FFFF8A2C [R/W] :$FF End-Mask 3 Hi
$FFFF8A2D [R/W] :$FF Lo
$FFFF8A2E [R/W] :$00 Destination-X-Increment Hi
$FFFF8A2F [R/W] :$04 Lo
$FFFF8A30 [R/W] :$00 Destination-Y-Increment Hi
$FFFF8A31 [R/W] :$54 Lo
$FFFF8A32 [R/W] :$00 ******
$FFFF8A33 [R/W] :$3F Destination-Address Hi
$FFFF8A34 [R/W] :$FD Mi
$FFFF8A35 [R/W] :$EA Lo
$FFFF8A36 [R/W] :$00 X-Count Hi
$FFFF8A37 [R/W] :$14 Lo
$FFFF8A38 [R/W] :$00 Y-Count Hi
$FFFF8A39 [R/W] :$00 Lo
$FFFF8A3A [R/W] :$01 Halftone-Operation
$FFFF8A3B [R/W] :$03 Logic-Operation
$FFFF8A3C [R/W] :$06 Line-Number
$FFFF8A3D [R/W] :$00 Skew
$FFFF8A3E [R/W] :$FF ******
$FFFF8A3F [R/W] :$FF ******
****************************************************************************
S E R I A L - C O M M U N I C A T I O N S - C O N T R O L L E R ( T T )
****************************************************************************
$FFFF8C80 [R/W] :$9F ******
$FFFF8C81 [R/W] :$EC Register Selection Channel A
$FFFF8C82 [R/W] :$FF ******
$FFFF8C83 [R/W] :$FF Read / Write Data Channel A
$FFFF8C84 [R/W] :$8F ******
$FFFF8C85 [R/W] :$44 Register Selection Channel B
$FFFF8C86 [R/W] :$FF ******
$FFFF8C87 [R/W] :$FF Read / Write Data Channel B
****************************************************************************
J O Y S T I C K / L I G H T P E N - P O R T S ( S T E )
****************************************************************************
$FFFF9200 [R/W] :$BF Fire-Buttons 1-4 Hi
$FFFF9201 [R/W] :$FF Lo
$FFFF9202 [R/W] :$FF Joysticks 1-4 Hi
$FFFF9203 [R/W] :$FF Lo
$FFFF9210 [R/W] :$8F Position Paddle 0 Hi
$FFFF9211 [R/W] :$FF Lo
$FFFF9212 [R/W] :$8F Position Paddle 1 Hi
$FFFF9213 [R/W] :$FF Lo
$FFFF9214 [R/W] :$8F Position Paddle 2 Hi
$FFFF9215 [R/W] :$FF Lo
$FFFF9216 [R/W] :$8F Position Paddle 3 Hi
$FFFF9217 [R/W] :$FF Lo
$FFFF9220 [R/W] :$00 Lightpen X-Position Hi
$FFFF9221 [R/W] :$00 Lo
$FFFF9222 [R/W] :$00 Lightpen Y-Position Hi
$FFFF9223 [R/W] :$00 Lo
****************************************************************************
2 5 6 C O L O R - R E G I S T E R S ( F A L C O N )
****************************************************************************
$FFFF9800 [R/W] :$FC 765432__ ................................ Color $00 Red
||||||
++++++------ 0-63: Red
$FFFF9801 [R/W] :$FC 765432__ .............................. Color $00 Green
||||||
++++++------ 0-63: Green
$FFFF9802 [R/W] :$00 ******
$FFFF9803 [R/W] :$00 765432__ ............................... Color $00 Blue
||||||
++++++------ 0-63: Blue
$FFFF9804 [R/W] :$FC Color $01 Red
$FFFF9805 [R/W] :$FC Color $01 Green
$FFFF9806 [R/W] :$00 ******
$FFFF9807 [R/W] :$00 Color $01 Blue
: : : :
: : : :
: : : :
$FFFF9BFC [R/W] :$00 Color $FF Red
$FFFF9BFD [R/W] :$00 Color $FF Green
$FFFF9BFE [R/W] :$00 ******
$FFFF9BFF [R/W] :$00 Color $FF Blue
****************************************************************************
D S P - H O S T - I N T E R F A C E ( FA L C O N )
****************************************************************************
$FFFFA200 [R/W] :$00 76543_10 ........................ Host-Control-Register
||||| ||
||||| |+---- 1: enable 'DSP-had-send'-IRQ
||||| +----- 1: enable 'DSP-ready to receive'-IRQ
||||+------- Hf2-Bit, userdef. Infobit from DSP to Host
|||+-------- Hf3-Bit, userdef. Infobit from DSP to Host
+++--------- set to zero
$FFFFA201 [R/W] :$12 <=====
$FFFFA202 [R/W] :$06 _6543_10 ..........................Host-Status-Register
|||| ||
|||| |+---- 0: DSP busy
|||| | 1: DSP had send
|||| +----- 0: DSP busy
|||| 1: DSP ready to receive
|||+------- Hf0-Bit, userdef. Infobit from Host to DSP
||+-------- Hf1-Bit, userdef. Infobit from Host to DSP
++--------- set to zero
$FFFFA203 [R/W] :$0F <=====
$FFFFA204 [R/W] :$00 ________ ............................. I/O-Data-Path HH
$FFFFA205 [R/W] :$00 76543210 ............................. Hi
$FFFFA206 [R/W] :$00 76543210 ............................. Mi
$FFFFA207 [R/W] :$00 76543210 ............................. Lo
$03FC-$03FF : DSP-IRQ-vector. This vector is used for receiving
or/and sending data from/to the DSP in interrupt-
mode.
HOW to send datawords to DSP in handshaking-technic:
1. step: wait until DSP ready to receive ($A202.w Bit 1 turns to 1)
2. step: write data to $A204.w-$A207.w
3. step: if you want to send once again>> goto 1. step
Example: This routine corresponds to the DSP-XBIOS:
LEA BUFFER(PC),A0 ;Buffer with DSP-Words
MOVE.W #DSP_WORDS,D0 ;transfer max. 65535 DSP-Words
LOOP: BTST #0,$FFFFA202.W ;is DSP ready to receive?
BEQ.S LOOP
4 bytes: 'MOVE.L (A0)+,$FFFFA204.W ;transfer 4 bytes
;the highest byte will be ignored
;by the DSP
3 bytes: 'MOVE.B (A0)+,$FFFFA205.W ;transfer
MOVE.B (A0)+,$FFFFA206.W ;3 bytes
MOVE.B (A0)+,$FFFFA207.W ;(1 DSP-Word has 24 Bit)
2 bytes: 'MOVE.W (A0)+,D1 ;get 2 bytes
EXT.L D1 ;sign-extension
MOVE.W D1,$FFFFA204.W ;transfer 4 bytes
1 byte: 'MOVE.B #0,$FFFFA205.W ;transfer
MOVE.B #0,$FFFFA206.W ;1 byte
MOVE.B (A0)+,$FFFFA207.W
DBRA D0,LOOP
HOW to receive datawords from DSP in handshaking-technic:
1. step: wait until DSP had send ($A202.w Bit 0 turns to 1)
2. step: read data from $A204.w-$A207.w
3. step: if you want to receive once again >> goto 1. step
Example: This routine corresponds to the DSP-XBIOS
LEA BUFFER(PC),A0 ;Buffer with DSP-Words
MOVE.W #DSP_WORDS,D0 ;transfer max. 65535 DSP-Words
LOOP: BTST #1,$FFFFA202.W ;had DSP send?
BEQ.S LOOP
4 bytes: 'MOVE.L $FFFFA204.W,(A0)+ ;transfer 4 bytes
;the highest byte is zero
3 bytes: 'MOVE.B $FFFFA205.W,(A0)+ ;transfer
MOVE.B $FFFFA206.W,(A0)+ ;3 bytes
MOVE.B $FFFFA207.W,(A0)+ ;(1 DSP-Word has 24 Bit)
2 bytes: 'MOVE.B $FFFFA206.W,(A0)+ ;transfer
MOVE.W $FFFFA207.W,(A0)+ ;2 bytes
1 byte: 'MOVE.B $FFFFA206.W,D1 ;dummy-read, nobody knows why.
MOVE.B $FFFFA207.W,(A0)+ ;transfer 1 byte
DBRA D0,LOOP
NOTE: it is possible to skip the 1. step. This mode increases the
transfering-rate, but the DSP-program must be able to read the data
immediately, otherwhise the data will be overwritten by the next
one. It is important that the DSP is ready to transfer, therefor
execute the 1. step before transfering data!
(1. step > 2. step > 2. step > 2. step ......until end)
HOW to send datawords to DSP in interrupt-technic:
1. step: IRQ-Instalation in special order:
1.: write the IRQ-program-address in the DSP-IRQ-vector
2.: write register $A203.w with $FF
3.: set bit 1 of Host-Control-Register
now the DSP-IRQ is installed and enabled!
2. step: the style of the IRQ-vector-routine:
1.: read data from $A204.w-$A207.w
2.: end the IRQ-routine with a RTE
3. step: you have two possibilities to stop the IRQ-transfer:
1.: you clear bit 1 in the main program
2.: you clear bit 1 in the IRQ-program
HOW to receive datawords fron DSP in interrupt-technic:
1. step: IRQ-Instalation in special order:
1.: write the IRQ-program-address in the DSP-IRQ-vector
2.: write register $A203.w with $FF
3.: set bit 0 of Host-Control-Register
now the DSP-IRQ is installed and enabled!
2. step: the style of the IRQ-vector-routine:
1.: write data to $A204.w-$A207.w
2.: end the IRQ-routine with a RTE
3. step: you have two possibilities to stop the IRQ-transfer:
1.: you clear bit 0 in the main program
2.: you clear bit 0 in the IRQ-program
NOTE: You have only one exception for sending and receiving data. But
it is possible to send and receive data simultanously. In the IRQ-
program you have to test bit 0/1 of the Host-Status-Register to
get information about the transfering direction!
****************************************************************************
M U L T I - F U N C T I O N - P E R I P H E R A L MC 68901 ( S T )
****************************************************************************
$FFFFFA00 [R/-] :$8F ******
$FFFFFA01 [R/W] :$ED GPIP-Data
$FFFFFA02 [R/-] :$8F ******
$FFFFFA03 [R/W] :$04 Active-Edge
$FFFFFA04 [R/-] :$8F ******
$FFFFFA05 [R/W] :$00 Data-Direction
$FFFFFA06 [R/-] :$8F ******
$FFFFFA07 [R/W] :$DE Interrupt-Enable A
$FFFFFA08 [R/-] :$8F ******
$FFFFFA09 [R/W] :$64 Interrupt-Enable B
$FFFFFA0A [R/-] :$8F ******
$FFFFFA0B [R/W] :$02 Interrupt-Pending A
$FFFFFA0C [R/-] :$8F ******
$FFFFFA0D [R/W] :$60 Interrupt-Pending B
$FFFFFA0E [R/-] :$8F ******
$FFFFFA0F [R/W] :$00 Interrupt-In-Service A
$FFFFFA10 [R/-] :$8F ******
$FFFFFA11 [R/W] :$00 Interrupt-In-Service B
$FFFFFA12 [R/-] :$8F ******
$FFFFFA13 [R/W] :$5E Interrupt-Mask A
$FFFFFA14 [R/-] :$8F ******
$FFFFFA15 [R/W] :$64 Interrupt-Mask B
$FFFFFA16 [R/-] :$8F ******
$FFFFFA17 [R/W] :$48 Interrupt-Vektor
$FFFFFA18 [R/-] :$FF ******
$FFFFFA19 [R/W] :$00 Timer-A-Control
$FFFFFA1A [R/-] :$8F ******
$FFFFFA1B [R/W] :$00 Timer-B-Control
$FFFFFA1C [R/-] :$8F ******
$FFFFFA1D [R/W] :$51 Timer-C+D-Control
$FFFFFA1E [R/-] :$8F ******
$FFFFFA1F [R/W] :$00 Timer-A-Data
$FFFFFA20 [R/-] :$8F ******
$FFFFFA21 [R/W] :$FF Timer-B-Data
$FFFFFA22 [R/-] :$9F ******
$FFFFFA23 [R/W] :$AA Timer-C-Data
$FFFFFA24 [R/-] :$8F ******
$FFFFFA25 [R/W] :$02 Timer-D-Data
$FFFFFA26 [R/-] :$8F ******
$FFFFFA27 [R/W] :$00 Synchronous-Character
$FFFFFA28 [R/-] :$8F ******
$FFFFFA29 [R/W] :$88 USART-Control
$FFFFFA2A [R/-] :$8F ******
$FFFFFA2B [R/W] :$09 Receiver-Status
$FFFFFA2C [R/-] :$FF ******
$FFFFFA2D [R/W] :$85 Transmitter-Status
$FFFFFA2E [R/-] :$CF ******
$FFFFFA2F [R/W] :$FF USART-Data
****************************************************************************
K E Y B O A R D / M I D I - A C I A S 6850 ( S T )
****************************************************************************
$FFFFFC00 [R/-] :$83 Keyboard-Status
[-/W] :$83 Keyboard-Control
$FFFFFC01 [R/-] :$FF ******
$FFFFFC02 [R/-] :$9C Keyboard-Receive
[-/W] :$9C Keyboard-Send
$FFFFFC03 [R/-] :$FF ******
$FFFFFC04 [R/-] :$02 Midi-Status
[-/W] :$02 Midi-Control
$FFFFFC05 [R/-] :$FF ******
$FFFFFC06 [R/-] :$02 Midi-Receive
[-/W] :$02 Midi-Send
$FFFFFC07 [R/-] :$FF ******
****************************************************************************
? ? ? ? ? ?
****************************************************************************
$FFFFFF82 [R/-] :$1C new
$FFFFFF83 [R/-] :$00 new
******************************** END OF FILE *******************************
