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1995-02-27
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374 lines
**
** Listing of all Motorola instructions supported by PhxAss V3.xx
**
** Integer Instructions (68000,68010,68020,68030,68040)
ABCD Dy,Dx Add Decimal with Extend
ABCD -(Ay),-(Ax)
ADD.x <ea>,Dn Add
ADD.x Dn,<ea>
ADDA.x <ea>,An Add Address
ADDI.x #<data>,<ea> Add Immediate
ADDQ.x #<data>,<ea> Add Quick
ADDX.x Dy,Dx Add Extended
ADDX.x -(Ay),-(Ax)
AND.x <ea>,Dn And Logical
AND.x Dn,<ea>
ANDI.x #<data>,<ea> And Immediate
ANDI.x #<data>,CCR And Immediate to Condition Codes
ANDI.x #<data>,SR And Immediate to the Status Register
ASL/ASR.x Dx,Dy Arithmetic Shift Left/Right
ASL/ASR.x #<data>,Dy
ASL/ASR <ea>
B<cc>.x <label> Branch Conditionally
BCHG Dn,<ea> Test a Bit and Change
BCHG #<data>,<ea>
BCLR Dn,<ea> Test a Bit and Clear
BCLR #<data>,<ea>
BRA.x <label> Branch Always
BSET Dn,<ea> Test a Bit and Set
BSET #<data>,<ea>
BSR.x <label> Branch to Subroutine
BTST.x Dn,<ea> Test a Bit
BTST.x #<data>,<ea>
CHK.x <ea>,Dn Check Register Against Bounds
CLR.x <ea> Clear an Operand
CMP.x <ea>,Dn Compare
CMPA.x <ea>,An Compare Address
CMPI.x #<data>,<ea> Compare Immediate
CMPM.x (Ay)+,(Ax)+ Compare Memory
DB<cc> Dn,<label> Test Condition, Decrement, and Branch
DIVS <ea>,Dn Signed Divide
DIVU <ea>,Dn Unsigned Divide
EOR.x Dn,<ea> Exclusive-OR Logical
EORI.x #<data>,<ea> Exclusive-OR Immediate
EORI.x #<data>,CCR Exclusive-OR Immediate to Cond. Codes
EORI.x #<data>,SR Exclusive-OR Immediate to Status Reg.
EXG Rn,Rm Exchange Registers
EXT.x Dn Sign Extend
ILLEGAL Take Illegal Instruction Trap
JMP <ea> Jump
JSR <ea> Jump to Subroutine
LEA <ea>,An Load Effective Address
LINK An,#<displacement> Link and Allocate
LSL/LSR.x Dx,Dy Logical Shift Left/Right
LSL/LSR.x #<data>,Dy
LSL/LSR <ea>
MOVE.x <ea>,<ea> Move Data from Source to Destination
MOVEA.x <ea>,An Move Address
MOVE <ea>,CCR Move to Condition Codes
MOVE <ea>,SR Move to the Status Register
MOVE SR,<ea> Move from Status Register
MOVE USP,An Move User Stack Pointer
MOVE An,USP
MOVEM.x <register list>,<ea> Move Multiple Registers
MOVEM.x <ea>,<register list>
MOVEP.x Dx,(d,Ay) Move Peripheral Data
MOVEP.x (d,Ay),Dx
MOVEQ #<data>,Dn Move Quick
MULS <ea>,Dn Signed Multiply
MULU <ea>,Dn Unsigned Multiply
NBCD <ea> Negate Decimal with Extend
NEG.x <ea> Negate
NEGX.x <ea> Negate with Extend
NOP No Operation
NOT.x <ea> Logical Complement
OR.x <ea>,Dn Inclusive-OR Logical
OR.x Dn,<ea>
ORI.x #<data>,<ea> Inclusive-OR Immediate
ORI.x #<data>,CCR Inclusive-OR Immediate to Cond. Codes
PEA <ea> Push Effective Address
RESET Reset External Devices
ROL/ROR.x Dx,Dy Rotate (without Extend) Left/Right
ROL/ROR.x #<data>,Dy
ROL/ROR <ea>
ROXL/ROXR.x Dx,Dy Rotate Left/Right with Extend
ROXL/ROXR.x #<data>,Dy
ROXL/ROXR <ea>
RTE Return from Exception
RTR Return and Restore Condition Codes
RTS Return from Subroutine
SBCD Dx,Dy Subtract Decimal with Extend
SBCD -(Ax),-(Ay)
S<cc> <ea> Set According to Condition
STOP #<data> Load Status Register and Stop
SUB.x <ea>,Dn Subtract
SUB.x Dn,<ea>
SUBA.x <ea>,An Subtract Address
SUBI.x #<data>,<ea> Subtract Immediate
SUBQ.x #<data>,<ea> Subtract Quick
SUBX.x Dx,Dy Subtract with Extend
SWAP Dn Swap Register Halves
TAS <ea> Test and Set an Operand
TRAP #<vector> Take Trap Exception
TRAPV Trap on Overflow
TST.x <ea> Test an Operand
UNLK An Unlink
Integer Condition Codes <cc>:
CC (HS) carry clear (higher or same) CS (LO) carry set (lower)
EQ equal F never true
GE greater or equal GT greater than
HI higher LE less or equal
LS less or same LT less than
MI negative NE not equal
PL positive T always true
VC overflow clear VS overflow set
** Integer Instructions (68010,68020,68030,68040)
BKPT #<data> Breakpoint
MOVE CCR,<ea> Move from the Condition Code Register
MOVEC Rc,Rn Move Control Registers
MOVEC Rn,Rc
MOVES Rn,<ea> Move Address Space
MOVES <ea>,Rn
RTD #<displacement> Return and Deallocate
** Integer Instructions (68020,68030,68040)
BFCHG <ea>{offset:width} Test Bit Field and Change
BFCLR <ea>{offset:width} Test Bit Field and Clear
BFEXTS <ea>{offset:width},Dn Extract Bit Field Signed
BFEXTU <ea>{offset:width},Dn Extract Bit Field Unsigned
BFFFO <ea>{offset:width},Dn Find First One in Bit Field
BFINS Dn,<ea>{offset:width} Insert Bit Field
BFSET <ea>{offset:width} Test Bit Field and Set
BFTST <ea>{offset:width} Test Bit Field
CALLM #<data>,<ea> Call Module (68020 ONLY!)
CAS.x Dc,Du,<ea> Compare and Swap with Operand
CAS2.x Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
CHK2.x <ea>,Rn Check Register Against Bounds
CMP2.x <ea>,Rn Compare Register Against Bounds
DIVS.L <ea>,Dq Signed Divide
DIVS.L <ea>,Dr:Dq
DIVSL.L <ea>,Dr:Dq
DIVU.L <ea>,Dq Unsigned Divide
DIVU.L <ea>,Dr:Dq
DIVUL.L <ea>,Dr:Dq
EXTB.L Dn Sign Extend
LINK.L An,#<displacement> Link and Allocate
MULS.L <ea>,Dl Signed Multiply
MULS.L <ea>,Dh:Dl
MULU.L <ea>,Dl Unsigned Multiply
MULU.L <ea>,Dh:Dl
PACK -(Ax),-(Ay),#<adjustment> Pack BCD
PACK Dx,Dy,#<adjustment>
RTM Rn Return from Module (68020 ONLY!)
TRAP<cc> Trap on Condition
TRAP<cc>.x #<data>
UNPK -(Ax),-(Ay),#<adjustment> Unpack BCD
UNPK Dx,Dy,#<adjustment>
** Integer Instructions (68040)
CINVL <caches>,(An) Invalidate Cache Lines
CINVP <caches>,(An) (<caches> = DC, IC, BC or NC)
CINVA <caches>
CPUSHL <caches>,(An) Push and Invalidate Cache Lines
CPUSHP <caches>,(An)
CPUSHA <caches>
MOVE16 (Ax)+,(Ay)+ Move 16 Bytes Block
MOVE16 xxx.L,(An)
MOVE16 xxx.L,(An)+
MOVE16 (An),xxx.L
MOVE16 (An)+,xxx.L
MOVEC Control Registers (Rc):
68010 68020 68030 68040
SFC Source Function Code x x x x
DFC Destination Function Code x x x x
USP User Stack Pointer x x x x
VBR Vector Base Register x x x x
CACR Cache Control Register x x x
CAAR Cache Address Register x x
MSP Master Stack Pointer x x x
ISP Interrupt Stack Pointer x x x
TC MMU Translation Control Register x
ITT0 Instr. Transparent Translation Reg. 0 x
ITT1 Instr. Transparent Translation Reg. 1 x
DTT0 Data Transparent Translation Reg. 0 x
DTT1 Data Transparent Translation Reg. 1 x
MMUSR MMU Status Register x
URP User Root Pointer x
SRP Supervisor Root Pointer x
** Floating Point Instructions (68881,68882,68040)
Monadic operations:
Fxxxx <ea>,FPn
Fxxxx FPm,FPn
Fxxxx FPn
FABS Floating-Point Absolute value
FACOS Arc Cosine
FASIN Arc Sine
FATAN Arc Tangent
FTANTH Hyberbolic Arc Tangent
FCOS Cosine
FCOSH Hyperbolic Cosine
FETOX e to x
FETOXM1 e to x minus one
FGETEXP Get Exponent
FGETMAN Get Mantissa
FINT Integer Part
FINTRZ Integer Part, Round to Zero
FLOG10 log10
FLOG2 log2
FLOGN loge
FLOGNP1 loge (x+1)
FNEG Floating-Point Negate
FSIN Sine
FSINH Hyperbolic Sine
FSQRT Floating-Point Square Root
FTAN Tangent
FTANH Hyperbolic Tangent
FTENTOX 10 to x
FTWOTOX 2 to x
Dyadic operations:
Fxxxx <ea>,FPn
Fxxxx FPm,FPn
FADD Floating-Point Add
FCMP Floating-Point Compare
FDIV Floating-Point Divide
FMOD Modulo Remainder
FMUL Floating-Point Multiply
FREM IEEE Remainder
FSCALE Scale Exponent
FSGLDIV Single Precision Divide
FSGLMUL Single Precision Multiply
FSUB Floating-Point Subtract
Special operations:
FB<cc>.x <label> Floating-Point Branch Conditionally
FDB<cc> Dn,<label> F.-Point Test Cond., Decr., and Branch
FMOVE.x <ea>,FPn Move Floating-Point Data Register
FMOVE.x FPm,<ea>
FMOVE.P FPm,<ea>{Dn}
FMOVE.P FPm,<ea>{#k}
FMOVE.L <ea>,FPcr Move Flt.-Point System Control Register
FMOVE.L FPcr,<ea> (FPcr = FPCR, FPSR or FPIAR)
FMOVECR #ccc,FPn Move Constant ROM
FMOVEM <list>,<ea> Move Multiple Flt.-Point Data Registers
FMOVEM Dn,<ea>
FMOVEM <ea>,<list>
FMOVEM <ea>,Dn
FMOVEM.L <list>,<ea> Move Multiple Flt.-Point Control Regs.
FMOVEM.L <ea>,<list> (<list> = combination of FPCR,FPSR,FPIAR)
FNOP No Operation
FRESTORE <ea> Restore Internal Floating-Point State
FSAVE <ea> Save Internal Floating-Point State
FS<cc> <ea> Set According to Flt.-Point Condition
FSINCOS.x <ea>,FPc:FPs Simultaneous Sine and Cosine
FSINCOS FPm,FPc:FPs
FTRAP<cc> Trap on Floating-Point Condition
FTRAP<cc>.x #<data>
FTST.x <ea> Test Floating-Point Operand
FTST FPm
Floating-Point Condition Codes <cc>:
F false EQ equal
OGT ordered greater than OGE ordered greater than or equal
OLT ordered less than OLE ordered less than or equal
OGL ordered greater or less than OR ordered
UN unordered UNE unordered or equal
UGT unordered or greater than UGE unordered or gt. than or equal
ULT unordered or less than ULE unordered or less than or equal
NE not equal T true
SF signaling false SEQ signaling equal
GT greater than GE greater than or equal
LT less than LE less than or equal
GL greater than or less than GLE greater or less than or equal
NGLE not (gt. or less or equal) NGL not (greater or less than)
NLE not (less than or equal) NLT not (less than)
NGE not (greater than or equal) NGT not (greater than)
SNE signaling not equal ST signaling true
** Floating Point Instructions (68040)
FSADD Add Single Precision
FDADD Add Double Precision
FSDIV Single Precision Divide
FDDIV Double Precision Divide
FSMOVE Single Precision Move
FDMOVE Double Precision Move
FSMUL Single Precision Multiply
FDMUL Double Precision Multiply
FSNEG Single Precision Negate
FDNEG Double Precision Negate
FSSQRT Single Precision Square Root
FDSQRT Double Precision Square Root
FSSUB Subtract Single Precision
FDSUB Subtract Double Precision
** PMMU Instructions (68851)
PB<cc>.x <label> Branch on PMMU Condition
PDB<cc> Dn,<label> Test, Decrement, and Branch on PMMU Cond.
PFLUSHA Invalidate Entries in the ATC
PFLUSH <fc>,#<mask>
PFLUSHS <fc>,#<mask>
PFLUSH <fc>,#<mask>,<ea>
PFLUSHS <fc>,#<mask>,<ea>
PFLUSHR <ea> Invalidate ATC and RPT Entries
PLOADR <fc>,<ea> Load an Entry into the ATC
PLOADW <fc>,<ea>
PMOVE <PMMU Register>,<ea> Move PMMU Register
PMOVE <ea>,<PMMU Register>
PRESTORE <ea> PMMU Restore Function
PSAVE <ea> PMMU Save Function
PS<cc> <ea> Set on PMMU Condition
PTESTR <fc>,<ea>,#<level> Get Information About Logical Address
PTESTR <fc>,<ea>,#<level>,An
PTESTW <fc>,<ea>,#<level>
PTESTW <fc>,<ea>,#<level>,An
PTRAP<cc> Trap on PMMU Condition
PTRAP<cc>.x #<data>
PMMU Condition Codes <cc>:
BS, BC, LS, LC, SS, SC, AS, AC, WS, WC, IS, IC, GS, GC, CS, CC
PMMU Registers:
CRP, SRP, DRP, TC, BACx, BADx, AC, PSR, PCSR, CAL, VAL, SCC
** PMMU Instructions (68030)
PFLUSHA Flush Entry in the ATC
PFLUSH <fc>,#<mask>
PFLUSH <fc>,#<mask>,<ea>
PLOADR <fc>,<ea> Load an Entry into the ATC
PLOADW <fc>,<ea>
PMOVE MRn,<ea> Move to/from MMU Registers
PMOVE <ea>,MRn
PMOVEFD <ea>,MRn
PTESTR <fc>,<ea>,#<level> Test a Logical Address
PTESTR <fc>,<ea>,#<level>,An
PTESTW <fc>,<ea>,#<level>
PTESTW <fc>,<ea>,#<level>,An
PMMU Registers (MRn):
SRP, CRP, TC, MMUSR(PSR), TT0, TT1
** PMMU Instructions (68040)
PFLUSH (An) Flush ATC Entries
PFLUSHN (An)
PFLUSHA
PFLUSHAN
PTESTR (An) Test a Logical Address
PTESTW (An)