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1998-03-08
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5KB
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263 lines
; binary.s
; --------
; Binary opcodes
GET hdr.common
GET hdr.memory
GET hdr.addressing
GBLS data1
GBLS data2
GBLS byte
GBLS address
; Update the Hu6280's N and Z flags from the ARM's N and Z flags
MACRO
update_flags
bic r_p, r_p, #N_FLAG + Z_FLAG
orreq r_p, r_p, #Z_FLAG
orrmi r_p, r_p, #N_FLAG
MEND
; AND two bytes
MACRO
m_and $and_reg
ands r_a, r_a, $and_reg
update_flags
MEND
; EOR two bytes
MACRO
m_eor $eor_reg
eors r_a, r_a, $eor_reg
update_flags
MEND
; OR two bytes
MACRO
m_ora $ora_reg
orrs r_a, r_a, $ora_reg
update_flags
MEND
; Arithmetic shift left
MACRO
m_asl $asl_reg
bic r_p, r_p, #N_FLAG + Z_FLAG + C_FLAG
movs $asl_reg, $asl_reg, lsl #1
orrcs r_p, r_p, #C_FLAG
orreq r_p, r_p, #Z_FLAG
orrmi r_p, r_p, #N_FLAG
MEND
; Logical shift right
MACRO
m_lsr $lsr_reg
bic r_p, r_p, #N_FLAG + Z_FLAG + C_FLAG
movs $lsr_reg, $lsr_reg, lsr #25
mov $lsr_reg, $lsr_reg, lsl #24
orrcs r_p, r_p, #C_FLAG
orreq r_p, r_p, #Z_FLAG
MEND
; Rotate left
MACRO
m_rol $rol_reg
tst r_p, #C_FLAG
orrne $rol_reg, $rol_reg, #1 << 23
movs $rol_reg, $rol_reg, lsl #1
bic r_p, r_p, #N_FLAG + Z_FLAG + C_FLAG
orrcs r_p, r_p, #C_FLAG
orreq r_p, r_p, #Z_FLAG
orrmi r_p, r_p, #N_FLAG
MEND
; Rotate right
MACRO
m_ror $ror_reg
movs $ror_reg, $ror_reg, lsr #25
orr $ror_reg, $ror_reg, r_p, lsl #7
bic r_p, r_p, #N_FLAG + Z_FLAG + C_FLAG
orrcs r_p, r_p, #C_FLAG
movs $ror_reg, $ror_reg, lsl #24
orreq r_p, r_p, #Z_FLAG
orrmi r_p, r_p, #N_FLAG
MEND
; Test memory bits against accumulator
MACRO
m_bit $bit_reg
NEW data1
bic r_p, r_p, #N_FLAG + V_FLAG + Z_FLAG
tst r_a, $bit_reg
orreq r_p, r_p, #Z_FLAG
and $data1, $bit_reg, #(N_FLAG + V_FLAG) << 24
orr r_p, r_p, $data1, lsr #24
DELETE data1
MEND
; Reset memory bit
MACRO
m_rmbi $rmbi_bit, $rmbi_byte
bic $rmbi_byte, $rmbi_byte, #(1 << $rmbi_bit) << 24
MEND
; Set memory bit
MACRO
m_smbi $smbi_bit, $smbi_byte
orr $smbi_byte, $smbi_byte, #(1 << $smbi_bit) << 24
MEND
; Test and set memory bits against accumulator
MACRO
m_tsb $tsb_reg
NEW data1
bic r_p, r_p, #N_FLAG + V_FLAG + Z_FLAG
and $data1, $tsb_reg, #(N_FLAG + V_FLAG) << 24
orrs $tsb_reg, $tsb_reg, r_a
orreq r_p, r_p, #Z_FLAG
orr r_p, r_p, $data1, lsr #24
DELETE data1
MEND
; Test and reset memory bits against accumulator
MACRO
m_trb $trb_reg
NEW data1
bic r_p, r_p, #N_FLAG + V_FLAG + Z_FLAG
and $data1, $trb_reg, #(N_FLAG + V_FLAG) << 24
bics $trb_reg, $trb_reg, r_a
orreq r_p, r_p, #Z_FLAG
orr r_p, r_p, $data1, lsr #24
DELETE data1
MEND
; Test and reset memory bits
MACRO
m_tst $mode
NEW data1
mr_im $data1
NEW data2
mr_$mode $data2
bic r_p, r_p, #N_FLAG + V_FLAG + Z_FLAG
ands $data2, $data2, $data1
orreq r_p, r_p, #Z_FLAG
and $data2, $data2, #(N_FLAG + V_FLAG) << 24
orr r_p, r_p, $data2, lsr #24
DELETE data1
DELETE data2
MEND
AREA |cpu$$opcodes|, CODE, READONLY
IMPORT Read_Register
IMPORT Write_Register
IMPORT Next_Opcode
OPCODE_R and, im, m_and
OPCODE_R and, zp, m_and
OPCODE_R and, zx, m_and
OPCODE_R and, in, m_and
OPCODE_R and, ix, m_and
OPCODE_R and, iy, m_and
OPCODE_R and, ab, m_and
OPCODE_R and, ax, m_and
OPCODE_R and, ay, m_and
OPCODE_RW asl, zp, m_asl
OPCODE_RW asl, zx, m_asl
OPCODE_RW asl, ab, m_asl
OPCODE_RW asl, ax, m_asl
DEF_OPCODE asl_rg
m_asl r_a
END_OPCODE
OPCODE_R bit, im, m_bit
OPCODE_R bit, zp, m_bit
OPCODE_R bit, zx, m_bit
OPCODE_R bit, ab, m_bit
OPCODE_R bit, ax, m_bit
OPCODE_R eor, im, m_eor
OPCODE_R eor, zp, m_eor
OPCODE_R eor, zx, m_eor
OPCODE_R eor, in, m_eor
OPCODE_R eor, ix, m_eor
OPCODE_R eor, iy, m_eor
OPCODE_R eor, ab, m_eor
OPCODE_R eor, ax, m_eor
OPCODE_R eor, ay, m_eor
OPCODE_RW lsr, zp, m_lsr
OPCODE_RW lsr, zx, m_lsr
OPCODE_RW lsr, ab, m_lsr
OPCODE_RW lsr, ax, m_lsr
DEF_OPCODE lsr_rg
m_lsr r_a
END_OPCODE
OPCODE_R ora, im, m_ora
OPCODE_R ora, zp, m_ora
OPCODE_R ora, zx, m_ora
OPCODE_R ora, in, m_ora
OPCODE_R ora, ix, m_ora
OPCODE_R ora, iy, m_ora
OPCODE_R ora, ab, m_ora
OPCODE_R ora, ax, m_ora
OPCODE_R ora, ay, m_ora
OPCODE_RW rol, zp, m_rol
OPCODE_RW rol, zx, m_rol
OPCODE_RW rol, ab, m_rol
OPCODE_RW rol, ax, m_rol
DEF_OPCODE rol_rg
m_rol r_a
END_OPCODE
OPCODE_RW ror, zp, m_ror
OPCODE_RW ror, zx, m_ror
OPCODE_RW ror, ab, m_ror
OPCODE_RW ror, ax, m_ror
DEF_OPCODE ror_rg
m_ror r_a
END_OPCODE
OPCODE_RW rmbi0, zp, "m_rmbi 0,"
OPCODE_RW rmbi1, zp, "m_rmbi 1,"
OPCODE_RW rmbi2, zp, "m_rmbi 2,"
OPCODE_RW rmbi3, zp, "m_rmbi 3,"
OPCODE_RW rmbi4, zp, "m_rmbi 4,"
OPCODE_RW rmbi5, zp, "m_rmbi 5,"
OPCODE_RW rmbi6, zp, "m_rmbi 6,"
OPCODE_RW rmbi7, zp, "m_rmbi 7,"
OPCODE_RW smbi0, zp, "m_smbi 0,"
OPCODE_RW smbi1, zp, "m_smbi 1,"
OPCODE_RW smbi2, zp, "m_smbi 2,"
OPCODE_RW smbi3, zp, "m_smbi 3,"
OPCODE_RW smbi4, zp, "m_smbi 4,"
OPCODE_RW smbi5, zp, "m_smbi 5,"
OPCODE_RW smbi6, zp, "m_smbi 6,"
OPCODE_RW smbi7, zp, "m_smbi 7,"
OPCODE_RW trb, zp, m_trb
OPCODE_RW trb, ab, m_trb
OPCODE_RW tsb, zp, m_tsb
OPCODE_RW tsb, ab, m_tsb
DEF_OPCODE tst_zp
m_tst zp
END_OPCODE
DEF_OPCODE tst_zx
m_tst zx
END_OPCODE
DEF_OPCODE tst_ab
m_tst ab
END_OPCODE
DEF_OPCODE tst_ax
m_tst ax
END_OPCODE
END