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1998-02-28
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3KB
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192 lines
; branches.s
; ----------
; Branches and other PC altering opcodes
GET hdr.common
GET hdr.memory
GET hdr.addressing
GBLS offset
GBLS brk_val
GBLS r_p_temp
; Jump relative to PC
MACRO
m_jr
NEW offset
read_byte_fast $offset
sub timer, timer, #1 << 16
add r_pc, r_pc, $offset, asr #8
DELETE offset
MEND
; Branch on bit reset
MACRO
m_bbri $bbri_bit, $bbri_byte
tst $bbri_byte, #(1 << $bbri_bit) << 24
addne r_pc, r_pc, #1 << 16
bne Next_Opcode
m_jr
MEND
; Branch on bit set
MACRO
m_bbsi $bbsi_bit, $bbsi_byte
tst $bbsi_byte, #(1 << $bbsi_bit) << 24
addeq r_pc, r_pc, #1 << 16
beq Next_Opcode
m_jr
MEND
; Branch on flag reset
MACRO
m_br $br_flag
tst r_p, #$br_flag
addne r_pc, r_pc, #1 << 16
bne Next_Opcode
m_jr
MEND
; Branch on flag set
MACRO
m_bs $bs_flag
tst r_p, #$bs_flag
addeq r_pc, r_pc, #1 << 16
beq Next_Opcode
m_jr
MEND
AREA |cpu$$opcodes|, CODE, READONLY
IMPORT Next_Opcode
OPCODE_R bbr0, zp, "m_bbri 0,"
OPCODE_R bbr1, zp, "m_bbri 1,"
OPCODE_R bbr2, zp, "m_bbri 2,"
OPCODE_R bbr3, zp, "m_bbri 3,"
OPCODE_R bbr4, zp, "m_bbri 4,"
OPCODE_R bbr5, zp, "m_bbri 5,"
OPCODE_R bbr6, zp, "m_bbri 6,"
OPCODE_R bbr7, zp, "m_bbri 7,"
OPCODE_R bbs0, zp, "m_bbsi 0,"
OPCODE_R bbs1, zp, "m_bbsi 1,"
OPCODE_R bbs2, zp, "m_bbsi 2,"
OPCODE_R bbs3, zp, "m_bbsi 3,"
OPCODE_R bbs4, zp, "m_bbsi 4,"
OPCODE_R bbs5, zp, "m_bbsi 5,"
OPCODE_R bbs6, zp, "m_bbsi 6,"
OPCODE_R bbs7, zp, "m_bbsi 7,"
DEF_OPCODE bcs_rg
m_bs C_FLAG
END_OPCODE
DEF_OPCODE beq_rg
m_bs Z_FLAG
END_OPCODE
DEF_OPCODE bvs_rg
m_bs V_FLAG
END_OPCODE
DEF_OPCODE bmi_rg
m_bs N_FLAG
END_OPCODE
DEF_OPCODE bcc_rg
m_br C_FLAG
END_OPCODE
DEF_OPCODE bne_rg
m_br Z_FLAG
END_OPCODE
DEF_OPCODE bvc_rg
m_br V_FLAG
END_OPCODE
DEF_OPCODE bpl_rg
m_br N_FLAG
END_OPCODE
DEF_OPCODE bra_rg
m_jr
END_OPCODE
; N.B. A BRK instruction cannot be disabled by setting the interrupt disable flag
DEF_OPCODE brk
add r_pc, r_pc, #1 << 16
write_word_sp r_pc
write_byte_sp r_p
NEW offset
ldr $offset, [rmemory, #7 * 4]
bic r_p, r_p, #D_FLAG
add $offset, $offset, #0xff00
orr r_p, r_p, #I_FLAG + B_FLAG ; disable interrupts, set BRK flag
bic r_p, r_p, #0x80 << 16 ; (and hence, clear internal IRQ enable bit)
ldrb r_pc, [$offset, #0xf6]
ldrb $offset, [$offset, #0xf7]
mov r_pc, r_pc, lsl #16
add r_pc, r_pc, $offset, lsl #24
DELETE offset
END_OPCODE
DEF_OPCODE bsr
write_word_sp r_pc
m_jr
END_OPCODE
DEF_OPCODE jmp_ab
NEW offset
read_word_fast $offset
mov r_pc, $offset
DELETE offset
END_OPCODE
DEF_OPCODE jmp_in
NEW offset
read_word_fast $offset
read_word r_pc, $offset
DELETE offset
END_OPCODE
DEF_OPCODE jmp_ix
NEW offset
read_word_fast $offset
add $offset, $offset, r_x, lsr #8
read_word r_pc, $offset
DELETE offset
END_OPCODE
DEF_OPCODE jsr
NEW offset
read_word_fast $offset
sub r_pc, r_pc, #1 << 16
write_word_sp r_pc
mov r_pc, $offset
DELETE offset
END_OPCODE
DEF_OPCODE rti
NEW r_p_temp
read_byte_sp $r_p_temp
bic r_p, r_p, #0xff
orr r_p, r_p, $r_p_temp
bic r_p, r_p, #T_FLAG ; *****
read_word_sp r_pc
tst r_p, #I_FLAG ; check restored I_FLAG
orreq r_p, r_p, #0x80 << 16
bicne r_p, r_p, #0x80 << 16 ; update internal IRQ enable bit
add r_pc, r_pc, #1 << 16
DELETE r_p_temp
END_OPCODE
DEF_OPCODE rts
read_word_sp r_pc
add r_pc, r_pc, #1 << 16
END_OPCODE
END