home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
The Datafile PD-CD 4
/
DATAFILE_PDCD4.iso
/
unix
/
unixlib36d
/
src
/
sys
/
s
/
_syslib
< prev
next >
Wrap
Text File
|
1994-02-27
|
15KB
|
604 lines
; /* _syslib.s (c) Copyright 1990 H.Rogers */
GET @.src.sys.s.asm_dec
AREA |C$$code|,CODE,READONLY
ENTRY
IMPORT |_main|
EXPORT |__main|
NAME __main
|__main|
SWI &20010 ; OS_GetEnv
MOV sp,a2
SUB sl,sp,#2048
LDR a4,[pc,#|__cli_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__himem_ptr|-.-8]
STR a2,[a4,#0]
LDR a4,[pc,#|__stack_ptr|-.-8]
STR sl,[a4,#0]
LDMIA a3,{a1,a2}
AND a2,a2,#&ff
LDR a3,[pc,#|__time_ptr|-.-8]
STMIA a3,{a1,a2}
LDR a4,[pc,#|__robase_ptr|-.-8]
LDR a1,[a4,#0]
LDR a4,[pc,#|__base_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__rwlimit_ptr|-.-8]
LDR a1,[a4,#0]
LDR a4,[pc,#|__lomem_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__break_ptr|-.-8]
STR a1,[a4,#0]
CMP sl,a1
MOVLSS pc,lr ; no stack - exit fast
ADD sl,sl,#256
MOV fp,#0
LDR a1,[pc,#|__alloca_list_ptr|-.-8]
CMP a1,#0
STRNE fp,[a1,#0]
B |_main|
IMPORT |Image$$RO$$Base|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$RW$$Limit|
EXPORT |__svccli| ; copy CLI in SVC mode
NAME __svccli
|__svccli|
LDR a2,[pc,#|__cli_ptr|-.-8]
LDR a2,[a2,#0]
MOV a4,lr
SWI &16 ; OS_EnterOS
|__svccli_l0|
LDRBT a3,[a2],#1
STRBT a3,[a1],#1
CMP a3,#0
BNE |__svccli_l0|
MOVS pc,a4 ; return to USR mode
|__cli_ptr|
DCD |__cli|
|__robase_ptr|
DCD |__robase|
|__base_ptr|
DCD |__base|
|__rwbase_ptr|
DCD |__rwbase|
|__rwlimit_ptr|
DCD |__rwlimit|
|__himem_ptr|
DCD |__himem|
|__lomem_ptr|
DCD |__lomem|
|__break_ptr|
DCD |__break|
|__stack_ptr|
DCD |__stack|
|__time_ptr|
DCD |__time|
IMPORT |__alloca_list|,WEAK
|__alloca_list_ptr|
DCD |__alloca_list|
IMPORT |__uname_dont_pack|,WEAK
EXPORT |__uname_dont_pack_ptr|
|__uname_dont_pack_ptr|
DCD |__uname_dont_pack|
EXPORT |__exit|
NAME __exit
|__exit|
MOV a3,a1
LDR a2,[pc,#|__exit_word|-.-8]
MOV a1,#0
SWI &11 ; OS_Exit - never returns
|__exit_word|
DCD &58454241
IMPORT |__vret|,WEAK
EXPORT |___vret|
|___vret|
DCD |__vret|
IMPORT |__stdioinit|,WEAK
EXPORT |___stdioinit|
|___stdioinit|
DCD |__stdioinit|
IMPORT |__stdioexit|,WEAK
EXPORT |___stdioexit|
|___stdioexit|
DCD |__stdioexit|
IMPORT |___main|, WEAK
EXPORT |___do_global_ctors|
|___do_global_ctors|
DCD |___main|
EXPORT |__rdenv|
NAME __rdenv
|__rdenv|
MOV ip,a2
MOV a2,#0
MOV a3,#0
MOV a4,#0
SWI &20040
STMVCIA ip,{a2,a3,a4}
MOVVC a1,#0
MOVS pc,lr
EXPORT |__wrenv|
NAME __wrenv
|__wrenv|
LDMIA a2,{a2,a3,a4}
SWI &20040
MOVVC a1,#0
MOVS pc,lr
EXPORT |x$divtest|
|x$divtest|
MOVS pc,lr
EXPORT |x$remainder|
NAME x$remainder
|x$remainder|
STMFD sp!,{lr}
BL |x$divide|
MOV a1,a2
LDMFD sp!,{pc}^
EXPORT |x$uremainder|
NAME x$uremainder
|x$uremainder|
STMFD sp!,{lr}
BL |x$udivide|
MOV a1,a2
LDMFD sp!,{pc}^
|x$overflow|
MVN a1,#0
MOVS pc,lr
EXPORT |x$udivide| ; a1 = a2 / a1; a2 = a2 % a1
NAME x$udivide
|x$udivide|
CMP a1,#1
BLO |x$overflow|
BEQ |x$divide_l0|
MOV ip,#0
MOVS a2,a2
BPL |x$divide_l1|
ORR ip,ip,#&20000000; ip bit &20000000 = -ve a2
MOVS a2,a2,LSR #1
ORRCS ip,ip,#&10000000; ip bit &10000000 = bit 0 of a2
B |x$divide_l1|
|x$divide_l0| ; a1 == 1
MOV a1,a2
MOV a2,#0
MOVS pc,lr
EXPORT |x$divide| ; a1 = a2 / a1; a2 = a2 % a1
NAME x$divide
|x$divide|
CMP a1,#1
BLO |x$overflow|
BEQ |x$divide_l0|
ANDS ip,a1,#&80000000
RSBMI a1,a1,#0
ANDS a3,a2,#&80000000
EOR ip,ip,a3
RSBMI a2,a2,#0
ORR ip,a3,ip,LSR #1 ; ip bit &40000000 = -ve division
; ip bit &80000000 = -ve remainder
|x$divide_l1|
MOV a3,#1
MOV a4,#0
CMP a2,a1
BLO |x$divide_b0|
CMP a2,a1,LSL #1
BLO |x$divide_b1|
CMP a2,a1,LSL #2
BLO |x$divide_b2|
CMP a2,a1,LSL #3
BLO |x$divide_b3|
CMP a2,a1,LSL #4
BLO |x$divide_b4|
CMP a2,a1,LSL #5
BLO |x$divide_b5|
CMP a2,a1,LSL #6
BLO |x$divide_b6|
CMP a2,a1,LSL #7
BLO |x$divide_b7|
CMP a2,a1,LSL #8
BLO |x$divide_b8|
CMP a2,a1,LSL #9
BLO |x$divide_b9|
CMP a2,a1,LSL #10
BLO |x$divide_b10|
CMP a2,a1,LSL #11
BLO |x$divide_b11|
CMP a2,a1,LSL #12
BLO |x$divide_b12|
CMP a2,a1,LSL #13
BLO |x$divide_b13|
CMP a2,a1,LSL #14
BLO |x$divide_b14|
CMP a2,a1,LSL #15
BLO |x$divide_b15|
CMP a2,a1,LSL #16
BLO |x$divide_b16|
CMP a2,a1,LSL #17
BLO |x$divide_b17|
CMP a2,a1,LSL #18
BLO |x$divide_b18|
CMP a2,a1,LSL #19
BLO |x$divide_b19|
CMP a2,a1,LSL #20
BLO |x$divide_b20|
CMP a2,a1,LSL #21
BLO |x$divide_b21|
CMP a2,a1,LSL #22
BLO |x$divide_b22|
CMP a2,a1,LSL #23
BLO |x$divide_b23|
CMP a2,a1,LSL #24
BLO |x$divide_b24|
CMP a2,a1,LSL #25
BLO |x$divide_b25|
CMP a2,a1,LSL #26
BLO |x$divide_b26|
CMP a2,a1,LSL #27
BLO |x$divide_b27|
CMP a2,a1,LSL #28
BLO |x$divide_b28|
CMP a2,a1,LSL #29
BLO |x$divide_b29|
CMP a2,a1,LSL #30
BLO |x$divide_b30|
CMP a2,a1,LSL #31
SUBHS a2,a2,a1,LSL #31
ADDHS a4,a4,a3,LSL #31
CMP a2,a1,LSL #30
SUBHS a2,a2,a1,LSL #30
ADDHS a4,a4,a3,LSL #30
|x$divide_b30|
CMP a2,a1,LSL #29
SUBHS a2,a2,a1,LSL #29
ADDHS a4,a4,a3,LSL #29
|x$divide_b29|
CMP a2,a1,LSL #28
SUBHS a2,a2,a1,LSL #28
ADDHS a4,a4,a3,LSL #28
|x$divide_b28|
CMP a2,a1,LSL #27
SUBHSS a2,a2,a1,LSL #27
ADDHS a4,a4,a3,LSL #27
|x$divide_b27|
CMP a2,a1,LSL #26
SUBHS a2,a2,a1,LSL #26
ADDHS a4,a4,a3,LSL #26
|x$divide_b26|
CMP a2,a1,LSL #25
SUBHS a2,a2,a1,LSL #25
ADDHS a4,a4,a3,LSL #25
|x$divide_b25|
CMP a2,a1,LSL #24
SUBHS a2,a2,a1,LSL #24
ADDHS a4,a4,a3,LSL #24
|x$divide_b24|
CMP a2,a1,LSL #23
SUBHS a2,a2,a1,LSL #23
ADDHS a4,a4,a3,LSL #23
|x$divide_b23|
CMP a2,a1,LSL #22
SUBHS a2,a2,a1,LSL #22
ADDHS a4,a4,a3,LSL #22
|x$divide_b22|
CMP a2,a1,LSL #21
SUBHS a2,a2,a1,LSL #21
ADDHS a4,a4,a3,LSL #21
|x$divide_b21|
CMP a2,a1,LSL #20
SUBHS a2,a2,a1,LSL #20